View XC236X_7820268.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet, v0.1, june 2007 microcontrollers XC236X 16/32-bit single-chip microcontroller with 32-bit performance
edition 2007-06 published by infineon technologies ag 81726 munich, germany ? 2007 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life -support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or ef fectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, v0.1, june 2007 microcontrollers XC236X 16/32-bit single-chip microcontroller with 32-bit performance
xc2365 xc2000 family derivatives preliminary data sheet v0.1, 2007-06 draft version XC236X revision history: v0.1, 2007-06 previous version(s): none page subjects (major changes since last revision) we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
xc2365 xc2000 family derivatives table of contents preliminary data sheet 3 v0.1, 2007-06 draft version 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin configuration and definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1 memory subsystem and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 external bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5 on-chip debug support (ocds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.6 capture/compare unit (capcom2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7 capture/compare units ccu6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.8 general purpose timer (gpt12e) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.9 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.10 a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.11 universal serial interface channel modules (usic) . . . . . . . . . . . . . . . . . 54 3.12 multican module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.13 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.14 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.15 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.16 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2.1 dc parameters for upper voltage area . . . . . . . . . . . . . . . . . . . . . . . . 70 4.2.2 dc parameters for lower voltage area . . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3 analog/digital converter parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.4 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.4.1 definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.4.2 on-chip flash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.4.3 external clock drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.4.4 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.4.5 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.1 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.2 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table of contents
XC236X 16/32-bit single-chip microcontroller with 32-bit performance xc2000 family preliminary data sheet 4 v0.1, 2007-06 draft version 1 summary of features for a quick overview or reference, the XC236X?s properties are listed here in a condensed way. ? high performance 16-bit cpu with 5-stage pipeline ? 15 ns instruction cycle time at 66 mhz cpu clock (single-cycle execution) ? 1-cycle 32-bit addition and subtraction with 40-bit result ? 1-cycle multiplication (16
xc2365 xc2000 family derivatives summary of features preliminary data sheet 5 v0.1, 2007-06 draft version ? on-chip multican interface (rev. 2.0b active) with 64 message objects (full can/basic can) on 3 can nodes and gateway functionality ? on-chip real time clock ? up to 12 mbytes external address space for code and data ? programmable external bus characteristics for different address ranges ? multiplexed or demultiplexed external address/data buses ? selectable address bus width ? 16-bit or 8-bit data bus width ? four programmable chip-select signals ? single power supply from 3.0 v to 5.5 v ? programmable watchdog timer and oscillator watchdog ? up to 75 general purpose i/o lines ? on-chip bootstrap loader ? supported by a large range of development tools like c-compilers, macro- assembler packages, emulators, evaluat ion boards, hll-debuggers, simulators, logic analyzer disassemblers, programming boards ? on-chip debug support via jtag interface ? 100-pin green lqfp package, 0.5 mm (19.7 mil) pitch ordering information the ordering code for infineon microcontrolle rs provides an exact reference to the required product. this ordering code identifies: ? the derivative itself, i.e. its function set, the temperature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes for the xc23 6x please refer to your responsible sales representative or your local distributor. this document describes several derivatives of the XC236X group. table 1 enumerates these derivatives and summarizes the differences. as this document refers to all of these derivatives, some descriptions may not apply to a specific product. for simplicity all versions are referred to by the term XC236X throughout this document.
xc2365 xc2000 family derivatives summary of features preliminary data sheet 6 v0.1, 2007-06 draft version table 1 XC236X derivative synopsis derivative 1) 1) this data sheet is valid for devices starting with and including design step aa. temp. range program memory psram 2) 2) all derivatives additionally provide 1 kbyte sbram, 2 kbytes dpram, and 16 kbytes dsram. ccu6 mod. adc 3) chan. 3) analog input channels are listed for each analog/digital converter module separately. interfaces sak-xc2365- 72f66l -40 c to 125
xc2365 xc2000 family derivatives general device information preliminary data sheet 7 v0.1, 2007-06 draft version 2 general device information the XC236X derivatives are high-performance members of the infineon xc2000 family of full featured single-chip cmos microcontrollers. these devices extend the functionality and performance of the c166 family in terms of instructions (mac unit), peripherals, and speed. they combine high cpu performance (up to 66 million instructions per second) with high peripheral functionality and enhanced io-capabilities. optimized peripherals can be adapted to the application?s requirements in a flexible way. these derivatives also provide clock generation via pll and internal or external clock sources, and various on-chip memory modul es such as program flash, program ram, and data ram. figure 1 logic symbol m c _ xc 2 x_ l ogsym b4 xc2xxx port 0 8 bit port 1 8 bit port 2 13 bit port 4 4 bit port 6 3 bit port 7 5 bit v agnd (1) v aref (1) v ddp (9) v ss (4) jtag 4 bit trst debug 2 bit v ddi (4) xtal1 xtal2 esr0 esr1 port 10 16 bit port 15 5 bit port 5 11 bit testm porst tref via port pins
xc2365 xc2000 family derivatives general device information preliminary data sheet 8 v0.1, 2007-06 draft version 2.1 pin configuration and definition the pins of the XC236X are described in detail in table 2 , including all their alternate functions. for explanations, please refer to the footnotes at the table?s end. figure 2 summarizes all pins in a condensed way, showing their location on the 4 sides of the package. figure 2 pin configuration (top view) mc_ xc2 x_ pin1 0 0 v ddpb 25 p5.3 24 p5.2 23 p5.0 22 v ag n d 21 20 19 p15.5 18 v ddpa 17 16 p15.0 15 p15.4 14 p6.2 13 p6.1 12 p6.0 11 v ddim 10 9 8 p7.3 7 6 5 p7.2 4 testm 3 v ddpb 2 v ss 1 p7.0 trs t v ar ef p15.6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 v ddpb es r0 es r1 por s t xta l 1 xta l 2 p1 . 7 p1 . 6 p1 . 5 p10.15 p1 . 4 p10.14 v ddi1 p1 . 3 p10.13 p10.12 p1 . 2 p10.11 p10.10 p1 . 1 p10.9 p10.8 p1 . 0 v ddpb v ss 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 p2.4 46 47 48 49 50 v ss v dd pb p5.8 p5.9 p5. 10 p5. 11 p5. 13 p5 . 1 5 p2. 12 p2. 11 v ddi1 p2.0 p2.1 p2.2 p4.0 p2.3 p4.1 p2.5 p4.2 p2.6 p4.3 v dd pb 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v ss v ddpb p0.0 p2.7 p0.1 p2.8 p2.9 p0.2 p10.0 p10.1 p10. 2 p0.4 v ddi1 tref p2.10 p10.3 p0.5 p10.4 p10.5 p0.6 p10.6 p10.7 p0.7 v ddpb xc2xxx p7.4 p7.1 p15.2 p0.3 p5 . 4 p5 . 5
xc2365 xc2000 family derivatives general device information preliminary data sheet 9 v0.1, 2007-06 draft version notes to pin definitions 1. ctrl. : the output signal for a port pin is selected via bitfield pc in the associated register px_iocry. output o0 is selected by setting the respective bitfield pc to 1x00 b , output o1 is selected by 1x01 b , etc. output signal oh is controlled by hardware. 2. type : indicates the employed pad type (st=standard pad, sp=special pad, dp=double pad, in=input pad, ps=power supply) and its power supply domain (a, b, m, 1). table 2 pin definitions and functions pin symbol ctrl. type function 3 testm iin/b testmode enable enables factory test modes, must be held high for normal operation (connect to v ddpb ). 4 p7.2 o0 / i st/b bit 2 of port 7, general purpose input/output emux0 o1 st/b external analog mux control output 0 tdi_c i st/b jtag test data input 5trst iin/b test-system reset input for normal system operation, pin trst should be held low. a high level at this pin at the rising edge of porst activates the XC236X?s debug system. in this case, pin trst must be driven low once to reset the debug system. 6 p7.0 o0 / i st/b bit 0 of port 7, general purpose input/output t3out o1 st/b gpt1 timer t3 toggle latch output t6out o2 st/b gpt2 timer t6 toggle latch output tdo oh st/b jtag test data output esr2_1 i st/b esr2 trigger input 1 7 p7.3 o0 / i st/b bit 3 of port 7, general purpose input/output emux1 o1 st/b external analog mux control output 1 u0c1_dout o2 st/b usic0 channel 1 shift data output u0c0_dout o3 st/b usic0 channel 0 shift data output tms_c i st/b jtag test mode selection input u0c1_dx0f i st/b usic0 channel 1 shift data input
xc2365 xc2000 family derivatives general device information preliminary data sheet 10 v0.1, 2007-06 draft version 8 p7.1 o0 / i st/b bit 1 of port 7, general purpose input/output extclk o1 st/b programmable clock signal output brkin_c i st/b ocds break signal input 9 p7.4 o0 / i st/b bit 4 of port 7, general purpose input/output emux2 o1 st/b external analog mux control output 2 u0c1_dout o2 st/b usic0 channel 1 shift data output u0c1_sclk o3 st/b usic0 channel 1 shift clock output tck_c i st/b jtag clock input u0c0_dx0d i st/b usic0 channel 0 shift data input u0c1_dx1e i st/b usic0 channel 1 shift clock input 11 p6.0 o0 / i st/a bit 0 of port 6, general purpose input/output emux0 o1 st/a external analog mux control output 0 u1c1_dout o2 st/a usic1 channel 1 shift data output brkout o3 st/a ocds break signal output adcx_ reqgtyc i st/a external request gate input for adc0/1 u1c1_dx0e i st/a usic1 channel 1 shift data input 12 p6.1 o0 / i st/a bit 1 of port 6, general purpose input/output emux1 o1 st/a external analog mux control output 1 t3out o2 st/a gpt1 timer t3 toggle latch output u1c1_dout o3 st/a usic1 channel 1 shift data output adcx_ reqtryc i st/a external request trigger input for adc0/1 13 p6.2 o0 / i st/a bit 2 of port 6, general purpose input/output emux2 o1 st/a external analog mux control output 2 t6out o2 st/a gpt2 timer t6 toggle latch output u1c1_sclk o3 st/a usic1 channel 1 shift clock output u1c1_dx1c i st/a usic1 channel 1 shift clock input 15 p15.0 i in/a bit 0 of port 15, general purpose input adc1_ch0 i in/a analog input channel 0 for adc1 table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 11 v0.1, 2007-06 draft version 16 p15.2 i in/a bit 2 of port 15, general purpose input adc1_ch2 i in/a analog input channel 2 for adc1 t5in i in/a gpt2 timer t5 count/gate input 17 p15.4 i in/a bit 4 of port 15, general purpose input adc1_ch4 i in/a analog input channel 4 for adc1 t6in i in/a gpt2 timer t6 count/gate input 18 p15.5 i in/a bit 5 of port 15, general purpose input adc1_ch5 i in/a analog input channel 5 for adc1 t6eud i in/a gpt2 timer t6 external up/down control input 19 p15.6 i in/a bit 6 of port 15, general purpose input adc1_ch6 i in/a analog input channel 6 for adc1 20 v aref - ps/a reference voltage for a/d converters adc0/1 21 v agnd - ps/a reference ground for a/d converters adc0/1 22 p5.0 i in/a bit 0 of port 5, general purpose input adc0_ch0 i in/a analog input channel 0 for adc0 23 p5.2 i in/a bit 2 of port 5, general purpose input adc0_ch2 i in/a analog input channel 2 for adc0 tdi_a i in/a jtag test data input 24 p5.3 i in/a bit 3 of port 5, general purpose input adc0_ch3 i in/a analog input channel 3 for adc0 t3in i in/a gpt1 timer t3 count/gate input 28 p5.4 i in/a bit 4 of port 5, general purpose input adc0_ch4 i in/a analog input channel 4 for adc0 t3eud i in/a gpt1 timer t3 external up/down control input tms_a i in/a jtag test mode selection input 29 p5.5 i in/a bit 5 of port 5, general purpose input adc0_ch5 i in/a analog input channel 5 for adc0 ccu60_ t12hrb iin/a external run control input for t12 of ccu60 table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 12 v0.1, 2007-06 draft version 30 p5.8 i in/a bit 8 of port 5, general purpose input adc0_ch8 i in/a analog input channel 8 for adc0 ccu6x_ t12hrc iin/a external run control input for t12 of ccu60/1 ccu6x_ t13hrc iin/a external run control input for t13 of ccu60/1 31 p5.9 i in/a bit 9 of port 5, general purpose input adc0_ch9 i in/a analog input channel 9 for adc0 cc2_t7in i in/a capcom2 timer t7 count input 32 p5.10 i in/a bit 10 of port 5, general purpose input adc0_ch10 i in/a analog input channel 10 for adc0 brkin_a iin/a ocds break signal input 33 p5.11 i in/a bit 11 of port 5, general purpose input adc0_ch11 i in/a analog input channel 11 for adc0 34 p5.13 i in/a bit 13 of port 5, general purpose input adc0_ch13 i in/a analog input channel 13 for adc0 ex0binb i in/a external interrupt trigger input 35 p5.15 i in/a bit 15 of port 5, general purpose input adc0_ch15 i in/a analog input channel 15 for adc0 36 p2.12 o0 / i st/b bit 12 of port 2, general purpose input/output u0c0_ selo4 o1 st/b usic0 channel 0 select/control 4 output u0c1_ selo3 o2 st/b usic0 channel 1 select/control 3 output ready i st/b external bus interface ready input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 13 v0.1, 2007-06 draft version 37 p2.11 o0 / i st/b bit 11 of port 2, general purpose input/output u0c0_ selo2 o1 st/b usic0 channel 0 select/control 2 output u0c1_ selo2 o2 st/b usic0 channel 1 select/control 2 output bhe /wrh oh st/b external bus interf. high-byte control output can operate either as byte high enable (bhe ) or as write strobe for high byte (wrh ). 39 p2.0 o0 / i st/b bit 0 of port 2, general purpose input/output ad13 oh / i st/b external bus interface address/data line 13 rxdc0c i st/b can node 0 receive data input 40 p2.1 o0 / i st/b bit 1 of port 2, general purpose input/output txdc0 o1 st/b can node 0 transmit data output ad14 oh / i st/b external bus interface address/data line 14 esr1_5 i st/b esr1 trigger input 5 ex0aina i st/b external interrupt trigger input 41 p2.2 o0 / i st/b bit 2 of port 2, general purpose input/output txdc1 o1 st/b can node 1 transmit data output ad15 oh / i st/b external bus interface address/data line 15 esr2_5 i st/b esr2 trigger input 5 ex1aina i st/b external interrupt trigger input 42 p4.0 o0 / i st/b bit 0 of port 4, general purpose input/output cc2_24 o3 / i st/b capcom2 cc24io capture inp./ compare out. cs0 oh st/b external bus interface chip select 0 output table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 14 v0.1, 2007-06 draft version 43 p2.3 o0 / i st/b bit 3 of port 2, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output cc2_16 o3 / i st/b capcom2 cc16io capture inp./ compare out. a16 oh st/b external bus interface address line 16 esr2_0 i st/b esr2 trigger input 0 u0c0_dx0e i st/b usic0 channel 0 shift data input u0c1_dx0d i st/b usic0 channel 1 shift data input note: not available in step aa. rxdc0a i st/b can node 0 receive data input 44 p4.1 o0 / i st/b bit 1 of port 4, general purpose input/output txdc2 o2 st/b can node 2 transmit data output cc2_25 o3 / i st/b capcom2 cc25io capture inp./ compare out. cs1 oh st/b external bus interface chip select 1 output 45 p2.4 o0 / i st/b bit 4 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output note: not available in step aa. txdc0 o2 st/b can node 0 transmit data output cc2_17 o3 / i st/b capcom2 cc17io capture inp./ compare out. a17 oh st/b external bus interface address line 17 esr1_0 i st/b esr1 trigger input 0 u0c0_dx0f i st/b usic0 channel 0 shift data input rxdc1a i st/b can node 1 receive data input 46 p2.5 o0 / i st/b bit 5 of port 2, general purpose input/output u0c0_ sclkout o1 st/b usic0 channel 0 shift clock output txdc0 o2 st/b can node 0 transmit data output cc2_18 o3 / i st/b capcom2 cc18io capture inp./ compare out. a18 oh st/b external bus interface address line 18 u0c0_dx1d i st/b usic0 channel 0 shift clock input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 15 v0.1, 2007-06 draft version 47 p4.2 o0 / i st/b bit 2 of port 4, general purpose input/output txdc2 o2 st/b can node 2 transmit data output cc2_26 o3 / i st/b capcom2 cc26io capture inp./ compare out. cs2 oh st/b external bus interface chip select 2 output t2in i st/b gpt1 timer t2 count/gate input 48 p2.6 o0 / i st/b bit 6 of port 2, general purpose input/output u0c0_ selo0 o1 st/b usic0 channel 0 select/control 0 output u0c1_ selo1 o2 st/b usic0 channel 1 select/control 1 output cc2_19 o3 / i st/b capcom2 cc19io capture inp./ compare out. a19 oh st/b external bus interface address line 19 u0c0_dx2d i st/b usic0 channel 0 shift control input rxdc0d i st/b can node 0 receive data input 49 p4.3 o0 / i st/b bit 3 of port 4, general purpose input/output cc2_27 o3 / i st/b capcom2 cc27io capture inp./ compare out. cs3 oh st/b external bus interface chip select 3 output rxdc2a i st/b can node 2 receive data input t2eud i st/b gpt1 timer t2 external up/down control input 53 p0.0 o0 / i st/b bit 0 of port 0, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output ccu61_ cc60 o3 / i st/b ccu61 channel 0 input/output a0 oh st/b external bus interface address line 0 u1c0_dx0a i st/b usic1 channel 0 shift data input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 16 v0.1, 2007-06 draft version 54 p2.7 o0 / i st/b bit 7 of port 2, general purpose input/output u0c1_ selo0 o1 st/b usic0 channel 1 select/control 0 output u0c0_ selo1 o2 st/b usic0 channel 0 select/control 1 output cc2_20 o3 / i st/b capcom2 cc20io capture inp./ compare out. a20 oh st/b external bus interface address line 20 u0c1_dx2c i st/b usic0 channel 1 shift control input rxdc1c i st/b can node 1 receive data input 55 p0.1 o0 / i st/b bit 1 of port 0, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output txdc0 o2 st/b can node 0 transmit data output ccu61_ cc61 o3 / i st/b ccu61 channel 1 input/output a1 oh st/b external bus interface address line 1 u1c0_dx0b i st/b usic1 channel 0 shift data input u1c0_dx1a i st/b usic1 channel 0 shift clock input 56 p2.8 o0 / i dp/b bit 8 of port 2, general purpose input/output u0c1_ sclkout o1 dp/b usic0 channel 1 shift clock output extclk o2 dp/b programmable clock signal output 1) cc2_21 o3 / i dp/b capcom2 cc21io capture inp./ compare out. a21 oh dp/b external bus interface address line 21 u0c1_dx1d i dp/b usic0 channel 1 shift clock input 57 p2.9 o0 / i st/b bit 9 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output txdc1 o2 st/b can node 1 transmit data output cc2_22 o3 / i st/b capcom2 cc22io capture inp./ compare out. a22 oh st/b external bus interface address line 22 dirin i st/b clock signal input tck_a i st/b jtag clock input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 17 v0.1, 2007-06 draft version 58 p0.2 o0 / i st/b bit 2 of port 0, general purpose input/output u1c0_ sclkout o1 st/b usic1 channel 0 shift clock output txdc0 o2 st/b can node 0 transmit data output ccu61_ cc62 o3 / i st/b ccu61 channel 2 input/output a2 oh st/b external bus interface address line 2 u1c0_dx1b i st/b usic1 channel 0 shift clock input 59 p10.0 o0 / i st/b bit 0 of port 10, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output ccu60_ cc60 o2 / i st/b ccu60 channel 0 input/output ad0 oh / i st/b external bus interface address/data line 0 u0c0_dx0a i st/b usic0 channel 0 shift data input u0c1_dx0a i st/b usic0 channel 1 shift data input 60 p10.1 o0 / i st/b bit 1 of port 10, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output ccu60_ cc61 o2 / i st/b ccu60 channel 1 input/output ad1 oh / i st/b external bus interface address/data line 1 u0c0_dx0b i st/b usic0 channel 0 shift data input u0c0_dx1a i st/b usic0 channel 0 shift clock input 61 p0.3 o0 / i st/b bit 3 of port 0, general purpose input/output u1c0_ selo0 o1 st/b usic1 channel 0 select/control 0 output u1c1_ selo1 o2 st/b usic1 channel 1 select/control 1 output ccu61_ cout60 o3 st/b ccu61 channel 0 output a3 oh st/b external bus interface address line 3 u1c0_dx2a i st/b usic1 channel 0 shift control input rxdc0b i st/b can node 0 receive data input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 18 v0.1, 2007-06 draft version 62 p10.2 o0 / i st/b bit 2 of port 10, general purpose input/output u0c0_ sclkout o1 st/b usic0 channel 0 shift clock output ccu60_ cc62 o2 / i st/b ccu60 channel 2 input/output ad2 oh / i st/b external bus interface address/data line 2 u0c0_dx1b i st/b usic0 channel 0 shift clock input 63 p0.4 o0 / i st/b bit 4 of port 0, general purpose input/output u1c1_ selo0 o1 st/b usic1 channel 1 select/control 0 output u1c0_ selo1 o2 st/b usic1 channel 0 select/control 1 output ccu61_ cout61 o3 st/b ccu61 channel 1 output a4 oh st/b external bus interface address line 4 u1c1_dx2a i st/b usic1 channel 1 shift control input rxdc1b i st/b can node 1 receive data input 65 tref io sp/1 control pin for core voltage generation connect tref to v ddpb to use the on-chip evrs. connect tref to v ddi1 for external core voltage supply (on-chip evrs off). 66 p2.10 o0 / i st/b bit 10 of port 2, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output u0c0_ selo3 o2 st/b usic0 channel 0 select/control 3 output cc2_23 o3 / i st/b capcom2 cc23io capture inp./ compare out. a23 oh st/b external bus interface address line 23 u0c1_dx0e i st/b usic0 channel 1 shift data input capin i st/b gpt2 register caprel capture input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 19 v0.1, 2007-06 draft version 67 p10.3 o0 / i st/b bit 3 of port 10, general purpose input/output ccu60_ cout60 o2 st/b ccu60 channel 0 output ad3 oh / i st/b external bus interface address/data line 3 u0c0_dx2a i st/b usic0 channel 0 shift control input u0c1_dx2a i st/b usic0 channel 1 shift control input 68 p0.5 o0 / i st/b bit 5 of port 0, general purpose input/output u1c1_ sclkout o1 st/b usic1 channel 1 shift clock output u1c0_ selo2 o2 st/b usic1 channel 0 select/control 2 output ccu61_ cout62 o3 st/b ccu61 channel 2 output a5 oh st/b external bus interface address line 5 u1c1_dx1a i st/b usic1 channel 1 shift clock input u1c0_dx1c i st/b usic1 channel 0 shift clock input 69 p10.4 o0 / i st/b bit 4 of port 10, general purpose input/output u0c0_ selo3 o1 st/b usic0 channel 0 select/control 3 output ccu60_ cout61 o2 st/b ccu60 channel 1 output ad4 oh / i st/b external bus interface address/data line 4 u0c0_dx2b i st/b usic0 channel 0 shift control input u0c1_dx2b i st/b usic0 channel 1 shift control input 70 p10.5 o0 / i st/b bit 5 of port 10, general purpose input/output u0c1_ sclkout o1 st/b usic0 channel 1 shift clock output ccu60_ cout62 o2 st/b ccu60 channel 2 output ad5 oh / i st/b external bus interface address/data line 5 u0c1_dx1b i st/b usic0 channel 1 shift clock input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 20 v0.1, 2007-06 draft version 71 p0.6 o0 / i st/b bit 6 of port 0, general purpose input/output u1c1_dout o1 st/b usic1 channel 1 shift data output txdc1 o2 st/b can node 1 transmit data output ccu61_ cout63 o3 st/b ccu61 channel 3 output a6 oh st/b external bus interface address line 6 u1c1_dx0a i st/b usic1 channel 1 shift data input ccu61_ ctrapa i st/b ccu61 emergency trap input u1c1_dx1b i st/b usic1 channel 1 shift clock input 72 p10.6 o0 / i st/b bit 6 of port 10, general purpose input/output u0c0_dout o1 st/b usic0 channel 0 shift data output u1c0_ selo0 o3 st/b usic1 channel 0 select/control 0 output ad6 oh / i st/b external bus interface address/data line 6 u0c0_dx0c i st/b usic0 channel 0 shift data input u1c0_dx2d i st/b usic1 channel 0 shift control input ccu60_ ctrapa i st/b ccu60 emergency trap input 73 p10.7 o0 / i st/b bit 7 of port 10, general purpose input/output u0c1_dout o1 st/b usic0 channel 1 shift data output ccu60_ cout63 o2 st/b ccu60 channel 3 output ad7 oh / i st/b external bus interface address/data line 7 u0c1_dx0b i st/b usic0 channel 1 shift data input ccu60_ ccpos0a i st/b ccu60 position input 0 table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 21 v0.1, 2007-06 draft version 74 p0.7 o0 / i st/b bit 7 of port 0, general purpose input/output u1c1_dout o1 st/b usic1 channel 1 shift data output u1c0_ selo3 o2 st/b usic1 channel 0 select/control 3 output a7 oh st/b external bus interface address line 7 u1c1_dx0b i st/b usic1 channel 1 shift data input ccu61_ ctrapb i st/b ccu61 emergency trap input 78 p1.0 o0 / i st/b bit 0 of port 1, general purpose input/output u1c0_ mclkout o1 st/b usic1 channel 0 master clock output u1c0_ selo4 o2 st/b usic1 channel 0 select/control 4 output a8 oh st/b external bus interface address line 8 esr1_3 i st/b esr1 trigger input 3 ex0bina i st/b external interrupt trigger input 79 p10.8 o0 / i st/b bit 8 of port 10, general purpose input/output u0c0_ mclkout o1 st/b usic0 channel 0 master clock output u0c1_ selo0 o2 st/b usic0 channel 1 select/control 0 output ad8 oh / i st/b external bus interface address/data line 8 ccu60_ ccpos1a i st/b ccu60 position input 1 u0c0_dx1c i st/b usic0 channel 0 shift clock input brkin_b i st/b ocds break signal input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 22 v0.1, 2007-06 draft version 80 p10.9 o0 / i st/b bit 9 of port 10, general purpose input/output u0c0_ selo4 o1 st/b usic0 channel 0 select/control 4 output u0c1_ mclkout o2 st/b usic0 channel 1 master clock output ad9 oh / i st/b external bus interface address/data line 9 ccu60_ ccpos2a i st/b ccu60 position input 2 tck_b i st/b jtag clock input 81 p1.1 o0 / i st/b bit 1 of port 1, general purpose input/output u1c0_ selo5 o2 st/b usic1 channel 0 select/control 5 output u2c1_dout o3 st/b usic2 channel 1 shift data output a9 oh st/b external bus interface address line 9 esr2_3 i st/b esr2 trigger input 3 ex1bina i st/b external interrupt trigger input u2c1_dx0c i st/b usic2 channel 1 shift data input 82 p10.10 o0 / i st/b bit 10 of port 10, general purpose input/output u0c0_ selo0 o1 st/b usic0 channel 0 select/control 0 output ccu60_ cout63 o2 st/b ccu60 channel 3 output ad10 oh / i st/b external bus interface address/data line 10 esr1_2 i st/b esr1 trigger input 2 u0c0_dx2c i st/b usic0 channel 0 shift control input tdi_b i st/b jtag test data input u0c1_dx1a i st/b usic0 channel 1 shift clock input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 23 v0.1, 2007-06 draft version 83 p10.11 o0 / i st/b bit 11 of port 10, general purpose input/output u1c0_ sclkout o1 st/b usic1 channel 0 shift clock output brkout o2 st/b ocds break signal output ad11 oh / i st/b external bus interface address/data line 11 u1c0_dx1d i st/b usic1 channel 0 shift clock input rxdc2b i st/b can node 2 receive data input tms_b i st/b jtag test mode selection input 84 p1.2 o0 / i st/b bit 2 of port 1, general purpose input/output u1c0_ selo6 o2 st/b usic1 channel 0 select/control 6 output u2c1_ sclkout o3 st/b usic2 channel 1 shift clock output a10 oh st/b external bus interface address line 10 esr1_4 i st/b esr1 trigger input 4 ccu61_ t12hrb i st/b external run control input for t12 of ccu61 ex2aina i st/b external interrupt trigger input u2c1_dx0d i st/b usic2 channel 1 shift data input u2c1_dx1c i st/b usic2 channel 1 shift clock input 85 p10.12 o0 / i st/b bit 12 of port 10, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output txdc2 o2 st/b can node 2 transmit data output tdo o3 st/b jtag test data output ad12 oh / i st/b external bus interface address/data line 12 u1c0_dx0c i st/b usic1 channel 0 shift data input u1c0_dx1e i st/b usic1 channel 0 shift clock input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 24 v0.1, 2007-06 draft version 86 p10.13 o0 / i st/b bit 13 of port 10, general purpose input/output u1c0_dout o1 st/b usic1 channel 0 shift data output u1c0_ selo3 o3 st/b usic1 channel 0 select/control 3 output wr /wrl oh st/b external bus interface write strobe output active for each external write access, when wr , active for ext. writes to the low byte, when wrl . u1c0_dx0d i st/b usic1 channel 0 shift data input 87 p1.3 o0 / i st/b bit 3 of port 1, general purpose input/output u1c0_ selo7 o2 st/b usic1 channel 0 select/control 7 output u2c0_ selo4 o3 st/b usic2 channel 0 select/control 4 output a11 oh st/b external bus interface address line 11 esr2_4 i st/b esr2 trigger input 4 ex3aina i st/b external interrupt trigger input 89 p10.14 o0 / i st/b bit 14 of port 10, general purpose input/output u1c0_ selo1 o1 st/b usic1 channel 0 select/control 1 output u0c1_dout o2 st/b usic0 channel 1 shift data output rd oh st/b external bus interface read strobe output esr2_2 i st/b esr2 trigger input 2 u0c1_dx0c i st/b usic0 channel 1 shift data input rxdc3c i st/b can node 3 receive data input 90 p1.4 o0 / i st/b bit 4 of port 1, general purpose input/output u1c1_ selo4 o2 st/b usic1 channel 1 select/control 4 output u2c0_ selo5 o3 st/b usic2 channel 0 select/control 5 output a12 oh st/b external bus interface address line 12 u2c0_dx2b i st/b usic2 channel 0 shift control input table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 25 v0.1, 2007-06 draft version 91 p10.15 o0 / i st/b bit 15 of port 10, general purpose input/output u1c0_ selo2 o1 st/b usic1 channel 0 select/control 2 output u0c1_dout o2 st/b usic0 channel 1 shift data output u1c0_dout o3 st/b usic1 channel 0 shift data output ale oh st/b external bus interf. addr. latch enable output u0c1_dx1c i st/b usic0 channel 1 shift clock input 92 p1.5 o0 / i st/b bit 5 of port 1, general purpose input/output u1c1_ selo3 o2 st/b usic1 channel 1 select/control 3 output brkout o3 st/b ocds break signal output a13 oh st/b external bus interface address line 13 u2c0_dx0c i st/b usic2 channel 0 shift data input 93 p1.6 o0 / i st/b bit 6 of port 1, general purpose input/output u1c1_ selo2 o2 st/b usic1 channel 1 select/control 2 output u2c0_dout o3 st/b usic2 channel 0 shift data output a14 oh st/b external bus interface address line 14 u2c0_dx0d i st/b usic2 channel 0 shift data input 94 p1.7 o0 / i st/b bit 7 of port 1, general purpose input/output u1c1_ mclkout o2 st/b usic1 channel 1 master clock output u2c0_ sclkout o3 st/b usic2 channel 0 shift clock output a15 oh st/b external bus interface address line 15 u2c0_dx1c i st/b usic2 channel 0 shift clock input 95 xtal2 o sp/1 crystal oscillator amplifier output 96 xtal1 i sp/1 crystal oscillator amplifier input to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. voltages on xtal1 must comply to the core supply voltage v ddi1 . table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives general device information preliminary data sheet 26 v0.1, 2007-06 draft version 97 porst iin/b power on reset input a low level at this pin resets the XC236X completely. a spike filter suppresses input pulses <10 ns. input pulses >100 ns safely pass the filter. the minimum duration for a safe recognition should be 120 ns. 98 esr1 o0 / i st/b external service request 1 ex0ainb i st/b external interrupt trigger input 99 esr0 o0 / i st/b external service request 0 note: after power-up, esr0 operates as open- drain bidirectional reset with a weak pull-up. 10 v ddim - ps/m digital core supply voltage for domain m decouple with a 680 nf ceramic capacitor. 38, 64, 88 v ddi1 - ps/1 digital core supply voltage for domain 1 decouple each with a 220 nf ceramic capacitor. all v ddi1 pins must be connected to each other. 14 v ddpa - ps/a digital pad supply voltage for domain a connect decoupling capacitors to adjacent v ddp / v ss pin pairs as close as possible to the pins. note: the a/d_converters and ports p5, p6, and p15 are fed from supply voltage v ddpa . 2, 25, 27, 50, 52, 75, 77, 100 v ddpb - ps/b digital pad supply voltage for domain b connect decoupling capacitors to adjacent v ddp / v ss pin pairs as close as possible to the pins. note: the on-chip voltage regulators and all ports except p5, p6, and p15 are fed from supply voltage v ddpb . 1, 26, 51, 76 v ss - ps/-- digital ground all v ss pins must be connected to the ground-line or ground-plane. 1) to generate the reference clock output for bus timing measurement, f sys must be selected as source for extclk and p2.8 must be selected as output pin. also the high-speed clock pad must be enabled. this configuration is referred to as reference clock output signal clkout. table 2 pin definitions and functions (cont?d) pin symbol ctrl. type function
xc2365 xc2000 family derivatives functional description preliminary data sheet 27 v0.1, 2007-06 draft version 3 functional description the architecture of the XC236X combines advantages of risc, cisc, and dsp processors with an advanced peripheral subsystem in a very well-balanced way. in addition, the on-chip memory blocks allow t he design of compact systems-on-silicon with maximum performance (computing, control, communication). the on-chip memory blocks (program code-memory and sram, dual-port ram, data sram) and the set of generic peripherals are connected to the cpu via separate buses. another bus, the lxbus, connects additional on-chip resources as well as external resources (see figure 3 ). this bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC236X. the following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC236X. figure 3 block diagram c166sv2 - core dpram 2 kbytes cpu pmu dmu brgen adc1 8-bit/ 10-bit 8 ch. usic0 2 ch., 64 x bu ffe r rs232, li n, spi, iic, iis rtc wdt interrupt & pec eb c lxbus control exte rn a l bu s control dsram 16 kbytes psram 8/16/32 kbytes system functions clock, reset , st and-by ram ocds debug support xtal interrupt bus peri ph er al data bus 5 p1 5 p7 p6 po rt 5 p4 p2 p1 p0 8 8 13 4 3 5 16 mc_XC236X_blockdiagram program flash 0 256 kbytes program flash 1 128/192/256 kbytes program flash 2 0/64 kbytes gpt t6 t5 t4 t3 t2 adc0 8-bit/ 10-bit 8 ch. cc2 t8 t7 multi can 3 ch. usic2 2 ch., 64 x buffer rs232, li n, spi, iic, iis usic1 2 ch., 64 x bu ffe r rs232, li n, spi, iic, iis ccu61 t13 t12 ccu60 t13 t12 lxb us imb p1 0 11
xc2365 xc2000 family derivatives functional description preliminary data sheet 28 v0.1, 2007-06 draft version 3.1 memory subsystem and organization the memory space of the XC236X is config ured in a von neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and i/o ports, are organized within the same linear address space. table 3 XC236X memory map address area start loc. end loc. area size 1) 1) the areas marked with ? xc2365 xc2000 family derivatives functional description preliminary data sheet 29 v0.1, 2007-06 draft version this common memory space includes 16 mbytes and is arranged as 256 segments of 64 kbytes each, where each segment consists of four data pages of 16 kbytes each. the entire memory space can be accessed byte wise or word wise. portions of the on-chip dpram and the register spaces (esfr/sfr) have additionally been made directly bit addressable. the internal data memory areas and the special function register areas (sfr and esfr) are mapped into segment 0, the system segment. the program management unit (pmu) handles all code fetches and, therefore, controls accesses to the program memories, such as flash memory and psram. the data management unit (dmu) handles all data transfers and, therefore, controls accesses to the dsram and the on-chip peripherals. both units (pmu and dmu) are connected via the high-speed system bus to exchange data. this is required if operands are read from program memory, code or data is written to the psram, code is fetched from external memory, or data is read from or written to external resources, including peripherals on the lxbus (such as usic or multican). the system bus allows concurrent two-way communication for maximum transfer performance. up to 32 kbytes of on-chip program sram (psram) are provided to store user code or data. the psram is accessed via the pmu and is therefore optimized for code fetches. a section of the psram with programmable size can be write-protected. note: the actual size of the psram depends on the chosen derivative (see table 1 ). 16 kbytes of on-chip data sram (dsram) are provided as a storage for general user data. the dsram is accessed via a separate interface and is, therefore, optimized for data accesses. 2 kbytes of on-chip dual-port ram (dpram) are provided as a storage for user defined variables, for the system stack, general purpose register banks. a register bank can consist of up to 16 word wide (r0 to r1 5) and/or byte wide (rl0, rh0, ?, rl7, rh7) so-called general purpose registers (gprs). the upper 256 bytes of the dpram are directly bit addressable. when used by a gpr, any location in the dpram is bit addressable. 1 kbyte of on-chip stand-by sram (sbram) is provided as a storage for system- relevant user data that must be preserved while the major part of the device is powered down. the sbram is accessed via a specific interface and is powered via domain m.
xc2365 xc2000 family derivatives functional description preliminary data sheet 30 v0.1, 2007-06 draft version 1024 bytes (2 512 bytes) of the address space are reserved for the special function register areas (sfr space and esfr space). sfrs are word wide registers which are used for controlling and monitoring functions of the different on-chip units. unused sfr addresses are reserved for future members of the xc2000 family. therefore, they should either not be accessed, or written with zeros, to ensure upward compatibility. in order to meet the needs of designs where more memory is required than is provided on chip, up to 12 mbytes (approximately, see table 3 ) of external ram and/or rom can be connected to the microcontroller. the extern al bus interface also provides access to external peripherals. up to 576 kbytes of on-chip flash memory store code, constant data, and control data. the on-chip flash memory consists of up to 3 modules with a maximum capacity of 256 kbytes each. each module is organized in 4-kbyte sectors. one 4-kbyte sector of flash module 0 is used internally to st ore operation control parameters and protection information. note: the actual size of the flash memo ry depends on the chosen derivative (see table 1 ). each sector can be separately write protected 1) , erased and programmed (in blocks of 128 bytes). the complete flash area can be read-protected. a user-defined password sequence temporarily unlocks protected area s. the flash modules combine 128-bit read accesses with protected and efficient writing algorithms for programming and erasing. dynamic error correction provides ex tremely high read data security for all read accesses. accesses to different flash modules can be executed in parallel. for timing characteristics, please refer to section 4.4.2 , for further flash parameters, please refer to section 5.3 . 1) to save control bits, sectors are clustered for protection purposes, they remain separate for programming/erasing.
xc2365 xc2000 family derivatives functional description preliminary data sheet 31 v0.1, 2007-06 draft version 3.2 external bus controller all of the external memory accesses are per formed by a particular on-chip external bus controller (ebc). the ebc also controls accesses to resources connected to the on-chip lxbus (multican and the usic modules). the lxbus is an internal representation of the external bus and allows accessing integrated peripherals and modules in the same way as external components. the ebc can be programmed either to single chip mode when no external memory is required, or to an external bus mode with the following possible selections 1) : ? address bus width with a range of 0 ? 24-bit ? data bus width 8-bit or 16-bit ? bus operation multiplexed or demultiplexed the bus interface uses port 10 and port 2 for addresses and data. in the demultiplexed bus modes, the lower addresses are separate ly output on port 0 and port 1. the number of active segment address lines is selectabl e, restricting the external address space to 8 mbytes ? 64 kbytes. this is required when interface lines shall be assigned to port 2. up to 4 external cs signals (3 windows plus default) can be generated and output on port 4 in order to save external glue logic. external modules can directly be connected to the common address/data bus and their individual select lines. important timing characteristics of the external bus interface have been made programmable (via registers tconcsx/fconcsx) to allow the user the adaption of a wide range of different types of memories and external peripherals. access to very slow memories or modules with varying access times is supported via a particular ?ready? function. the active level of the control input signal is selectable. in addition, up to 4 independent address windows may be defined (via registers addrselx) which control accesses to resour ces with different bus characteristics. these address windows are arranged hierarchically where window 4 overrides window 3, and window 2 overrides window 1. all accesses to locations not covered by these 4 address windows are controlled by tconcs0/fconcs0. the currently active window can generate a chip select signal. the external bus timing is related to the rising edge of the reference clock output clkout. the external bus protocol is compat ible with that of the standard c166 family. 1) bus modes are switched dynamically if several address windows with different mode settings are used.
xc2365 xc2000 family derivatives functional description preliminary data sheet 32 v0.1, 2007-06 draft version 3.3 central processing unit (cpu) the main core of the cpu consists of a 5-stage execution pipeline with a 2-stage instruction-fetch pipeline, a 16-bit arithmetic and logic unit (alu), a 32-bit/40-bit multiply and accumulate unit (mac), a register-file providing three register banks, and dedicated sfrs. the alu features a multiply and divide unit, a bit-mask generator, and a barrel shifter. figure 4 cpu block diagram dpram cpu ipip rf r0 r1 gprs r14 r15 r0 r1 gprs r14 r15 ifu injection/ exception handler adu mac mca04917_x.vsd cpucon1 cpucon2 csp ip return stack fifo branch unit prefetch unit vecseg tfr +/- idx0 idx1 qx0 qx1 qr0 qr1 dpp0 dpp1 dpp2 dpp3 spseg sp stkov stkun +/- mrw mcw msw mal +/- mah multiply unit alu division unit multiply unit bit-mask-gen. barrel-shifter +/- mdc psw mdh zeros mdl ones r0 r1 gprs r14 r15 cp wb buffer 2-stage prefetch pipeline 5-stage pipeline r0 r1 gprs r14 r15 pmu dmu dsram ebc peripherals psram flash/rom
xc2365 xc2000 family derivatives functional description preliminary data sheet 33 v0.1, 2007-06 draft version based on these hardware provisions, most of the XC236X?s instructions can be executed in just one machine cycle which requires 15 ns at 66 mhz cpu clock. for example, shift and rotate instructions are always proc essed during one machine cycle independent of the number of bits to be shifted. also mult iplication and most mac instructions execute in one single cycle. all multiple-cycle instruct ions have been optimized so that they can be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles, while the remaining cycles are execut ed in the background. another pipeline optimization, the branch target prediction, allows eliminating the execution time of branch instructions if the prediction was correct. the cpu has a register context consisting of up to three register banks with 16 word wide gprs each at its disposal. one of these register banks is physically allocated within the on-chip dpram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu at any time. the number of these register bank copies is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. a system stack of up to 32 kwords is pr ovided as a storage for temporary data. the system stack can be allocated to any location within the address space (preferably in the on-chip ram area), and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, ar e implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. the high performance offered by the hardware implementation of the cpu can efficiently be utilized by a programmer via the highly efficient XC236X instruction set which includes the following instruction classes: ? standard arithmetic instructions ? dsp-oriented arithmetic instructions ? logical instructions ? boolean bit manipulation instructions ? compare and loop control instructions ? shift and rotate instructions ? prioritize instruction ? data movement instructions ? system stack instructions ? jump and call instructions ? return instructions ? system control instructions ? miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possible operand types are bits, bytes and words. a variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
xc2365 xc2000 family derivatives functional description preliminary data sheet 34 v0.1, 2007-06 draft version 3.4 interrupt system with an interrupt response time of typically 8 cpu clocks (in case of internal program execution), the XC236X is capable of reacting very fast to the occurrence of non- deterministic events. the architecture of the XC236X supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. any of t hese interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ?stolen? from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source, or the destination pointer, or both. an individual pec transfer counter is implicitly decremented for each pec service except when performing in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. pec services are very well suited, for example, for supporting the transmission or reception of blocks of data. the XC236X has 8 pec channels each of which offers such fast interrupt-driven data transfer capabilities. a separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bit field exists for each of the possible interrupt nodes. via its related register, each node can be programmed to one of sixteen interrupt priority levels. once having been accepted by th e cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt nodes has a dedicated vector location. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast interrupt inputs feature programmable edge detection (rising edge, falling edge, or both edges). software interrupts are supported by means of the ?trap? instruction in combination with an individual trap (interrupt) number. table 4 shows all of the possible XC236X interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. note: interrupt nodes which are not assigned to peripherals (unassigned nodes), may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xir).
xc2365 xc2000 family derivatives functional description preliminary data sheet 35 v0.1, 2007-06 draft version table 4 XC236X interrupt nodes source of interrupt or pec service request control register vector location 1) trap number capcom register 16, or eru request 0 cc2_cc16ic xx?0040 h 10 h / 16 d capcom register 17, or eru request 1 cc2_cc17ic xx?0044 h 11 h / 17 d capcom register 18, or eru request 2 cc2_cc18ic xx?0048 h 12 h / 18 d capcom register 19, or eru request 3 cc2_cc19ic xx?004c h 13 h / 19 d capcom register 20, or usic0 request 6 cc2_cc20ic xx?0050 h 14 h / 20 d capcom register 21, or usic0 request 7 cc2_cc21ic xx?0054 h 15 h / 21 d capcom register 22, or usic1 request 6 cc2_cc22ic xx?0058 h 16 h / 22 d capcom register 23, or usic1 request 7 cc2_cc23ic xx?005c h 17 h / 23 d capcom register 24, or eru request 0 cc2_cc24ic xx?0060 h 18 h / 24 d capcom register 25, or eru request 1 cc2_cc25ic xx?0064 h 19 h / 25 d capcom register 26, or eru request 2 cc2_cc26ic xx?0068 h 1a h / 26 d capcom register 27, or eru request 3 cc2_cc27ic xx?006c h 1b h / 27 d capcom register 28, or usic2 request 6 cc2_cc28ic xx?0070 h 1c h / 28 d capcom register 29, or usic2 request 7 cc2_cc29ic xx?0074 h 1d h / 29 d capcom register 30 cc2_cc30ic xx?0078 h 1e h / 30 d capcom register 31 cc2_cc31ic xx?007c h 1f h / 31 d gpt1 timer 2 gpt12e_t2ic xx?0080 h 20 h / 32 d gpt1 timer 3 gpt12e_t3ic xx?0084 h 21 h / 33 d gpt1 timer 4 gpt12e_t4ic xx?0088 h 22 h / 34 d
xc2365 xc2000 family derivatives functional description preliminary data sheet 36 v0.1, 2007-06 draft version gpt2 timer 5 gpt12e_t5ic xx?008c h 23 h / 35 d gpt2 timer 6 gpt12e_t6ic xx?0090 h 24 h / 36 d gpt2 caprel register gpt12e_cric xx?0094 h 25 h / 37 d capcom timer 7 cc2_t7ic xx?0098 h 26 h / 38 d capcom timer 8 cc2_t8ic xx?009c h 27 h / 39 d a/d converter request 0 adc_0ic xx?00a0 h 28 h / 40 d a/d converter request 1 adc_1ic xx?00a4 h 29 h / 41 d a/d converter request 2 adc_2ic xx?00a8 h 2a h / 42 d a/d converter request 3 adc_3ic xx?00ac h 2b h / 43 d a/d converter request 4 adc_4ic xx?00b0 h 2c h / 44 d a/d converter request 5 adc_5ic xx?00b4 h 2d h / 45 d a/d converter request 6 adc_6ic xx?00b8 h 2e h / 46 d a/d converter request 7 adc_7ic xx?00bc h 2f h / 47 d ccu60 request 0 ccu60_0ic xx?00c0 h 30 h / 48 d ccu60 request 1 ccu60_1ic xx?00c4 h 31 h / 49 d ccu60 request 2 ccu60_2ic xx?00c8 h 32 h / 50 d ccu60 request 3 ccu60_3ic xx?00cc h 33 h / 51 d ccu61 request 0 ccu61_0ic xx?00d0 h 34 h / 52 d ccu61 request 1 ccu61_1ic xx?00d4 h 35 h / 53 d ccu61 request 2 ccu61_2ic xx?00d8 h 36 h / 54 d ccu61 request 3 ccu61_3ic xx?00dc h 37 h / 55 d unassigned node ? xx?00e0 h 38 h / 56 d unassigned node ? xx?00e4 h 39 h / 57 d unassigned node ? xx?00e8 h 3a h / 58 d unassigned node ? xx?00ec h 3b h / 59 d unassigned node ? xx?00f0 h 3c h / 60 d unassigned node ? xx?00f4 h 3d h / 61 d unassigned node ? xx?00f8 h 3e h / 62 d unassigned node ? xx?00fc h 3f h / 63 d can request 0 can_0ic xx?0100 h 40 h / 64 d table 4 XC236X interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number
xc2365 xc2000 family derivatives functional description preliminary data sheet 37 v0.1, 2007-06 draft version can request 1 can_1ic xx?0104 h 41 h / 65 d can request 2 can_2ic xx?0108 h 42 h / 66 d can request 3 can_3ic xx?010c h 43 h / 67 d can request 4 can_4ic xx?0110 h 44 h / 68 d can request 5 can_5ic xx?0114 h 45 h / 69 d can request 6 can_6ic xx?0118 h 46 h / 70 d can request 7 can_7ic xx?011c h 47 h / 71 d can request 8 can_8ic xx?0120 h 48 h / 72 d can request 9 can_9ic xx?0124 h 49 h / 73 d can request 10 can_10ic xx?0128 h 4a h / 74 d can request 11 can_11ic xx?012c h 4b h / 75 d can request 12 can_12ic xx?0130 h 4c h / 76 d can request 13 can_13ic xx?0134 h 4d h / 77 d can request 14 can_14ic xx?0138 h 4e h / 78 d can request 15 can_15ic xx?013c h 4f h / 79 d usic0 request 0 u0c0_0ic xx?0140 h 50 h / 80 d usic0 request 1 u0c0_1ic xx?0144 h 51 h / 81 d usic0 request 2 u0c0_2ic xx?0148 h 52 h / 82 d usic0 request 3 u0c1_0ic xx?014c h 53 h / 83 d usic0 request 4 u0c1_1ic xx?0150 h 54 h / 84 d usic0 request 5 u0c1_2ic xx?0154 h 55 h / 85 d usic1 request 0 u1c0_0ic xx?0158 h 56 h / 86 d usic1 request 1 u1c0_1ic xx?015c h 57 h / 87 d usic1 request 2 u1c0_2ic xx?0160 h 58 h / 88 d usic1 request 3 u1c1_0ic xx?0164 h 59 h / 89 d usic1 request 4 u1c1_1ic xx?0168 h 5a h / 90 d usic1 request 5 u1c1_2ic xx?016c h 5b h / 91 d usic2 request 0 u2c0_0ic xx?0170 h 5c h / 92 d usic2 request 1 u2c0_1ic xx?0174 h 5d h / 93 d usic2 request 2 u2c0_2ic xx?0178 h 5e h / 94 d table 4 XC236X interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number
xc2365 xc2000 family derivatives functional description preliminary data sheet 38 v0.1, 2007-06 draft version usic2 request 3 u2c1_0ic xx?017c h 5f h / 95 d usic2 request 4 u2c1_1ic xx?0180 h 60 h / 96 d usic2 request 5 u2c1_2ic xx?0184 h 61 h / 97 d unassigned node ? xx?0188 h 62 h / 98 d unassigned node ? xx?018c h 63 h / 99 d unassigned node ? xx?0190 h 64 h / 100 d unassigned node ? xx?0194 h 65 h / 101 d unassigned node ? xx?0198 h 66 h / 102 d unassigned node ? xx?019c h 67 h / 103 d unassigned node ? xx?01a0 h 68 h / 104 d unassigned node ? xx?01a4 h 69 h / 105 d unassigned node ? xx?01a8 h 6a h / 106 d scu request 1 scu_1ic xx?01ac h 6b h / 107 d scu request 0 scu_0ic xx?01b0 h 6c h / 108 d program flash modules pfm_ic xx?01b4 h 6d h / 109 d rtc rtc_ic xx?01b8 h 6e h / 110 d end of pec subchannel eopic xx?01bc h 6f h / 111 d 1) register vecseg defines the segment where the vector table is located to. bitfield vecsc in register cpucon1 defines the distance between two adjacent vectors. this table represents the default setting, with a distance of 4 (two words) between two vectors. table 4 XC236X interrupt nodes (cont?d) source of interrupt or pec service request control register vector location 1) trap number
xc2365 xc2000 family derivatives functional description preliminary data sheet 39 v0.1, 2007-06 draft version the XC236X also provides an excellent me chanism to identify and to process exceptions or error conditions that arise during run-time, so-called ?hardware traps?. hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. table 5 shows all of the possible exceptions or error conditions that can arise during run- time: table 5 hardware trap summary exception condition trap flag trap vector vector location 1) 1) register vecseg defines the segment where the vector table is located to. bitfield vecsc in register cpucon1 defines the distance between two adjacent vectors. this table represents the default setting, with a distance of 4 (two words) between two vectors. trap number trap priority reset functions ? reset xx?0000 h 00 h iii class a hardware traps: ? system request 0 ? stack overflow ? stack underflow ? software break sr0 stkof stkuf softbrk sr0trap stotrap stutrap sbrktrap xx?0008 h xx?0010 h xx?0018 h xx?0020 h 02 h 04 h 06 h 08 h ii ii ii ii class b hardware traps: ? system request 1 ? undefined opcode ? memory access error ? protected instruction fault ? illegal word operand access sr1 undopc acer prtflt illopa btrap btrap btrap btrap btrap xx?0028 h xx?0028 h xx?0028 h xx?0028 h xx?0028 h 0a h 0a h 0a h 0a h 0a h i i i i i reserved ? ? [2c h - 3c h ][0b h - 0f h ] ? software traps: ? trap instruction ?? any [xx?0000 h - xx?01fc h ] in steps of 4 h any [00 h - 7f h ] current cpu priority
xc2365 xc2000 family derivatives functional description preliminary data sheet 40 v0.1, 2007-06 draft version 3.5 on-chip debug support (ocds) the on-chip debug support system provides a broad r ange of debug and emulation features built into the XC236X. the user software running on the XC236X can thus be debugged within the target system environment. the ocds is controlled by an external debugging device via the debug interface, consisting of the ieee-1149-conforming jtag port and a break interface. the debugger controls the ocds via a set of dedicated registers accessible via the jtag interface. additionally, the ocds system can be controlled by the cpu, e.g. by a monitor program. an injection interface allows the execution of ocds-generat ed instructions by the cpu. multiple breakpoints can be triggered by on-chip hardware, by software, or by an external trigger input. single stepping is supported as well as the injection of arbitrary instructions and read/write access to the complete internal address space. a breakpoint trigger can be answered with a cpu-halt, a monitor call, a data transfer, or/and the activation of an external signal. tracing data can be obtained via the jtag inte rface or via the external bus interface for increased performance. the debug interface uses a set of 6 interface signals (4 jtag lines, 2 optional break lines) to communicate with external circuitry.
xc2365 xc2000 family derivatives functional description preliminary data sheet 41 v0.1, 2007-06 draft version 3.6 capture/compare unit (capcom2) the capcom2 unit supports generation an d control of timing sequences on up to 16 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered mode). the capcom2 unit is typically used to handle high speed i/o tasks such as pulse and waveform generation, pulse width modulation (pwm), digital to analog (d/a) conversion, software timing, or time recording relative to external events. two 16-bit timers (t7/t8) with reload registers provide two independent time bases for the capture/compare register array. the input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer t6 in module gpt2. this provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specif ic requirements. in addition, an external count input for capcom2 timer t7 allows event scheduling for the capture/compare registers relative to external events. the capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either capcom2 timer t7 or t8 and programmed for capture or compare function. 12 registers of the capcom2 module have each one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. when a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (?captured?) into the capture/compare table 6 compare modes (capcom2) compare modes function mode 0 interrupt-only compare mode; several compare interrupts per timer period are possible mode 1 pin toggles on each compare match; several compare events per timer period are possible mode 2 interrupt-only compare mode; only one compare interrupt per timer period is generated mode 3 pin set ?1? on match; pin reset ?0? on compare timer overflow; only one compare event per timer period is generated double register mode two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible single event mode generates single edges or pulses; can be used with any compare mode
xc2365 xc2000 family derivatives functional description preliminary data sheet 42 v0.1, 2007-06 draft version register in response to an external event at the port pin which is associated with this register. in addition, a specific interrupt r equest for this capture/compare register is generated. either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. the contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. when a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.
xc2365 xc2000 family derivatives functional description preliminary data sheet 43 v0.1, 2007-06 draft version figure 5 capcom2 unit block diagram sixteen 16-bit capture/ compare registers mode control (capture or compare) t7 input control t8 input control mcb05569_2 ccxirq ccxirq ccxirq capcom2 provides channels x = 16 ? 31. (see signals ccxio and ccxirq) t7irq t8irq ccxio ccxio ccxio t7in t6ouf f cc t6ouf f cc reload reg. t7rel timer t7 timer t8 reload reg. t8rel
xc2365 xc2000 family derivatives functional description preliminary data sheet 44 v0.1, 2007-06 draft version 3.7 capture/compare units ccu6x the XC236X features two ccu6 units (ccu60, ccu61). the ccu6 is a high-resolution capture and compare unit with application specific modes. it provides inputs to start the timers sync hronously, an important feature in devices with several ccu6 modules. the module provides two independent timers (t12, t13), that can be used for pwm generation, especially for ac-motor control. additionally, special control modes for block commutation and multi-phase machines are supported. timer 12 features ? three capture/compare channels, each channel can be used either as capture or as compare channel. ? generation of a three-phase pwm supported (six outputs, individual signals for high- side and low-side switches) ? 16 bit resolution, maximum count frequency = peripheral clock ? dead-time control for each channel to avoid short-circuits in the power stage ? concurrent update of the required t12/13 registers ? center-aligned and edge-aligned pwm can be generated ? single-shot mode supported ? many interrupt request sources ? hysteresis-like control mode ? automatic start on an hw event (t12hr, for synchronization purposes) timer 13 features ? one independent compare channel with one output ? 16 bit resolution, maximum count frequency = peripheral clock ? can be synchronized to t12 ? interrupt generation at period-match and compare-match ? single-shot mode supported ? automatic start on an hw event (t13hr, for synchronization purposes) additional features ? block commutation for brushless dc-drives implemented ? position detection via hall-sensor pattern ? automatic rotational speed measurement for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac-drives ? output levels can be selected and adapted to the power stage
xc2365 xc2000 family derivatives functional description preliminary data sheet 45 v0.1, 2007-06 draft version figure 6 ccu6 block diagram timer t12 can work in capture and/or compare mode for its three channels. the modes can also be combined. timer t13 can work in compare mode only. the multi-channel control unit generates output patterns that c an be modulated by timer t12 and/or timer t13. the modulation sources can be selected and combined for the signal modulation. mc_ccu6_blockdiagram. vsd channel 0 channel 1 channel 2 t12 dead- time control input / output control cc62 cout62 cc61 cout61 cc60 cout60 cout63 ctrap channel 3 t13 ccpos0 1 1 1 2 2 2 1 start compare capt ure 3 multi- channel control trap control com pare compa re compa re compa re 1 t rap i nput ccpos1 ccpos2 output select output select 3 hal l i nput ccu6 module kernel f sys interrupts txhr
xc2365 xc2000 family derivatives functional description preliminary data sheet 46 v0.1, 2007-06 draft version 3.8 general purpose timer (gpt12e) unit the gpt12e unit represents a very flexible multifunctional timer/counter structure which may be used for many different time rela ted tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gpt12e unit incorporates five 16-bit timers which are organized in two separate modules, gpt1 and gpt2. each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. each of the three timers t2, t3, t4 of module gpt1 can be configured individually for one of four basic modes of operation, wh ich are timer, gated timer, counter, and incremental interface mode. in timer mode, the input clock for a timer is derived from the system clock, divided by a programmable prescaler, while counter mode allows a timer to be clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode, where the operation of a timer is controlled by the ?gat e? level on an external input pin. for these purposes, each timer has one associated port pin (txin) which serves as gate or clock input. the maximum resolution of the timers in module gpt1 is 4 system clock cycles. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud) to facilitate e.g. position tracking. in incremental interface mode the gpt1 timers (t2, t3, t4) can be directly connected to the incremental position sensor signals a and b via their respective inputs txin and txeud. direction and count signals are internally derived from these two input signals, so the contents of the respective timer tx co rresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has an output toggle latch (t3otl ) which changes its state on each timer overflow/underflow. the state of this latch may be output on pin t3out e.g. for time out monitoring of external hardware components. it may also be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is reloaded with the contents of t2 or t4 triggered either by an external signal or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated without software intervention.
xc2365 xc2000 family derivatives functional description preliminary data sheet 47 v0.1, 2007-06 draft version figure 7 block diagram of gpt1 mca05563 aux. timer t2 2 n :1 t2 mode control capture u/d basic clock f gpt t3con.bps1 t3otl t3out toggle latch t2in t2eud reload core timer t3 t3 mode control t3in t3eud u/d interrupt request (t3irq) t4 mode control u/d aux. timer t4 t4eud t4in reload capture interrupt request (t4irq) interrupt request (t2irq)
xc2365 xc2000 family derivatives functional description preliminary data sheet 48 v0.1, 2007-06 draft version with its maximum resolution of 2 system clock cycles, the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both time rs can be clocked with an input clock which is derived from the cpu clock via a programmabl e prescaler or with external signals. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud). concatenation of the timers is supported via the output toggle latch (t6otl) of timer t6, which changes its state on each timer overflow/underflow. the state of this latch may be used to clock timer t5, and/or it may be output on pin t6out. the overflows/underflows of timer t6 can additionally be used to clock the capcom2 timers, and to cause a reload from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture procedure. this allows the XC236X to measure absolute time differences or to perform pulse multiplication without software overhead. the capture trigger (timer t5 to caprel) may also be generated upon transitions of gpt1 timer t3?s inputs t3in and/or t3eud. this is especially advantageous when t3 operates in incremental interface mode.
xc2365 xc2000 family derivatives functional description preliminary data sheet 49 v0.1, 2007-06 draft version figure 8 block diagram of gpt2 mca05564 gpt2 timer t5 2 n :1 t5 mode control gpt2 caprel t3in/ t3eud caprel mode control t6 mode control reload clear u/d capture clear u/d t5in capin interrupt request (t5irq) interrupt request (t6irq) interrupt request (crirq) basic clock f gpt t6con.bps2 t6in gpt2 timer t6 t6otl t6ou t t6ouf toggle ff
xc2365 xc2000 family derivatives functional description preliminary data sheet 50 v0.1, 2007-06 draft version 3.9 real time clock the real time clock (rtc) module of the XC236X can be clocked with a selectable clock signal from internal sources or external sources (pins). the rtc basically consists of a chain of divider blocks: ? selectable 32:1 and 8:1 dividers (on - off) ? the reloadable 16-bit timer t14 ? the 32-bit rtc timer block (accessible via registers rtch and rtcl), made of: ? a reloadable 10-bit timer ? a reloadable 6-bit timer ? a reloadable 6-bit timer ? a reloadable 10-bit timer all timers count up. each timer can generate an interrupt request. all requests are combined to a common node request. figure 9 rtc block diagram note: the registers associated with the rtc are only affected by a power reset. cnt-register rel-register 10 bits 6 bits 6 bits 10 bits t14 mcb05568b t14-register interrupt sub node rtcint mux 32 pre run cnt int3 cnt int2 cnt int1 cnt int0 f cnt f rtc t14rel 10 bits 6 bits 6 bits 10 bits : mux 8 : refclk
xc2365 xc2000 family derivatives functional description preliminary data sheet 51 v0.1, 2007-06 draft version the rtc module can be used for different purposes: ? system clock to determine the current time and date ? cyclic time based interrupt, to prov ide a system time tick independent of cpu frequency and other resources ? 48-bit timer for long term measurements ? alarm interrupt upon a defined time
xc2365 xc2000 family derivatives functional description preliminary data sheet 52 v0.1, 2007-06 draft version 3.10 a/d converters for analog signal measurement, up to two 10-bit a/d converters (adc0, adc1) with 8 multiplexed input channels including a sample and hold circuit have been integrated on- chip. they use the method of successive approximation. the sample time (for loading the capacitors) and the conversion time ar e programmable and can thus be adjusted to the external circuitry. the a/d converters can also operate in 8-bit conversion mode, where the conversion time is further reduced. several independent conversion result registers, selectable interrupt requests, and highly flexible conversion s equences provide a high degree of programmability to fulfill the requirements of the respective application. both modules can be synchronized to allow parallel sampling of two input channels. for applications that require more analog input channels, external analog multiplexers can be controlled automatically. for applications that require less analog input channels, the remaining channel inputs can be used as digital input port pins. the a/d converters of the XC236X support two types of request sources which can be triggered by several internal and external events. ? parallel requests are activated at the same time and then executed in a predefined sequence. ? queued requests are executed in a user-defined sequence. in addition, the conversion of a specific channel can be inserted into a running sequence without disturbing this sequence. all requests ar e arbitrated according to the priority level that has been assigned to them. data reduction features, such as limit checking or result accumulation, reduce the number of required cpu accesses and so allow the precise evaluation of analog inputs (high conversion rate) even at low cpu speed. the peripheral event controller (pec) may be used to control the a/d converters or to automatically store conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. therefore, each a/d converter contains 8 result registers which can be concatenated to build a result fifo. wait-for-read mode can be enabled for each result register to prevent loss of conversion data. in order to decouple analog inputs from digi tal noise and to avoid input trigger noise those pins used for analog input can be disc onnected from the digital input stages under software control. this can be selected for each pin separately via registers p5_didis and p15_didis (port x digital input disable). the auto-power-down feature of the a/d converters minimizes the power consumption when no conversion is in progress.
xc2365 xc2000 family derivatives functional description preliminary data sheet 53 v0.1, 2007-06 draft version 3.11 universal serial interface channel modules (usic) the XC236X features three usic modules (usic0, usic1, usic2), each providing two serial communication channels. the universal serial interface channel (usic) module is based on a generic data shift and data storage structure which is identical for all supported serial communication protocols. each channel supports complete full-duplex operation with a basic data buffer structure (one transmit buffer and two receive buffer stages). in addition, the data handling software can use fifos. the protocol part (generation of shift clock/data/control signals) is independent from the general part and is handled by protocol-specific preprocessors (ppps). the usic?s input/output lines are connected to pins by a pin routing unit, so the inputs and outputs of each usic channel can be assigned to different interface pins providing great flexibility to the application software. all assignments can be done during runtime. figure 10 general structure of a usic module the regular structure of the usic module brings the following advantages: ? higher flexibility through configuration with same look-and-feel for data management ? reduced complexity for low-level drivers serving different protocols ? wide range of protocols, but improved performances (baud rate, buffer handling) usic_basic.vsd bus interface dbu 0 dbu 1 control 0 control 1 dsu 0 dsu 1 ppp_a ppp_b ppp_c ppp_d ppp_a ppp_b ppp_c ppp_d pin routing shell buffer & shift structure protocol preprocessors pins bus f sys fractional dividers baud rate generators
xc2365 xc2000 family derivatives functional description preliminary data sheet 54 v0.1, 2007-06 draft version target protocols each usic channel can receive and transmit data frames with a selectable data word width from 1 to 16 bits in each of the following protocols: ? uart (asynchronous serial channel) ? maximum baud rate: f sys / 4 ? data frame length programmable from 1 to 63 bits ? msb or lsb first ? lin support (local interconnect network) ? maximum baud rate: f sys / 16 ? checksum generation under software control ? baud rate detection possible by built-in capture event of baud rate generator ? ssc/spi/qspi (synchronous serial channel with or without data buffer) ? maximum baud rate in slave mode: f sys ? maximum baud rate in master mode: f sys / 2 ? number of data bits programmable from 1 to 63, more with explicit stop condition ? msb or lsb first ? optional control of slave select signals ? iic (inter-ic bus) ? supports baud rates of 100 kbit/s and 400 kbit/s ? iis (inter-ic sound bus) ? maximum baud rate: f sys / 2 for transmitter, f sys for receiver note: depending on the selected functions (such as digital filters, input synchronization stages, sample point adjustment, etc.), the maximum reachable baud rate can be limited. please also take care about additional delays, such as internal or external propagation delays and driver delays (e.g. for collision detection in uart mode, for iic, etc.).
xc2365 xc2000 family derivatives functional description preliminary data sheet 55 v0.1, 2007-06 draft version 3.12 multican module the multican module contains three independently operating can nodes with full-can functionality which are able to exchange data and remote frames via a gateway function. transmission and reception of can fr ames is handled in accordance with can specification v2.0 b (active). each can node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. all can nodes share a common set of up to 64 message objects. each message object can be individually allocated to one of the can nodes. besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the can nodes or to setup a fifo buffer. the message objects are organized in double-chained linked lists, where each can node has its own list of message objects. a can node stores frames only into message objects that are allocated to its own messa ge object list, and it transmits only messages belonging to this message object list. a powerful, command-driven list controller performs all message object list operations. figure 11 block diagram of multican module mc_multican_block3.vsd multican module kernel interrupt control f can port control can node 1 can contr ol message object buffer 64 objects can node 0 linked list control clock control address decoder can node 2 txdc2 rxdc2 txdc1 rxdc1 txdc0 rxdc0
xc2365 xc2000 family derivatives functional description preliminary data sheet 56 v0.1, 2007-06 draft version multican features ? can functionality conforms to can specification v2.0 b active for each can node (compliant to iso 11898) ? three independent can nodes ? 64 independent message objects (shared by the can nodes) ? dedicated control registers for each can node ? data transfer rate up to 1 mbit/s, individually programmable for each node ? flexible and powerful message transfer control and error handling capabilities ? full-can functionality for message objects: ? can be assigned to one of the can nodes ? configurable as transmit or receive objects, or as message buffer fifo ? handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering ? remote monitoring mode, and frame counter for monitoring ? automatic gateway mode support ? 16 individually programmable interrupt nodes ? analyzer mode for can bus monitoring
xc2365 xc2000 family derivatives functional description preliminary data sheet 57 v0.1, 2007-06 draft version 3.13 watchdog timer the watchdog timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. the watchdog timer is always enabled after an application reset of the chip, and can be disabled and enabled at any time by execut ing instructions diswdt and enwdt. the software has to be designed to service the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates a prewarning interrupt and then a reset request. the watchdog timer is a 16-bit timer, clock ed with the system clock divided by 16,384 or 256. the watchdog timer register is set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the watchdog timer is reloaded and the prescaler is cleared. thus, time intervals between 3.9
xc2365 xc2000 family derivatives functional description preliminary data sheet 58 v0.1, 2007-06 draft version 3.14 clock generation the clock generation unit can generate the system clock signal f sys for the XC236X with high flexibility from several external or internal clock sources. ? external clock signals on pad- or core-voltage level ? external crystal controlled by on-chip oscillator ? on-chip clock source for operation without crystal ? wake-up clock (ultra-low power) to further reduce power consumption the programmable on-chip pll with multiple prescalers generates a clock signal for maximum system performance from standard cr ystals or from the on-chip clock source. see also section 4.4.1 . the oscillator watchdog (owd) generates an interrupt if the crystal oscillator frequency falls below a certain limit or stops completely. in this case, the system can be supplied with an emergency clock to enable operation even after an external clock failure. all available clock signals can also be output on one of two selectable pins.
xc2365 xc2000 family derivatives functional description preliminary data sheet 59 v0.1, 2007-06 draft version 3.15 parallel ports the XC236X provides up to 75 i/o lines whic h are organized into 7 input/output ports and 2 input ports. all port lines are bit-addr essable, and all input/output lines can be individually (bit-wise) configured via port contro l registers. this configuration selects the direction (input/output), push/pull or open-dr ain operation, activation of pull devices, and edge characteristics (shape) and driver characteristics (output current) of the port drivers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. during the internal reset, all port pins are configured as inputs without pull devices active. all port lines have programmable alternate input or output functions associated with them. these alternate functions can be assigne d to various port pins to support the optimal utilization for a given application. for this reason, certain functions appear several times in table 7 . all port lines that are not used for these alternate functions may be used as general purpose i/o lines. table 7 summary of the XC236X?s parallel ports port width alternate functions port 0 8 address lines, serial interface lines of usic1, can0, and can1, input/output lines for ccu61 port 1 8 address lines, serial interface lines of usic1 and usic2, ocds control, interrupts port 2 13 address and/or data lines, bus control, serial interface lines of usic0, can0, and can1, input/output lines for ccu60 and capcom2, timer control signals, jtag, interrupts, system clock output port 4 4 chip select signals, serial interface lines of can2, input/output lines for capcom2, timer control signals port 5 11 analog input channels to adc0, input/output lines for ccu6x, timer control signals, jtag, ocds control, interrupts
xc2365 xc2000 family derivatives functional description preliminary data sheet 60 v0.1, 2007-06 draft version port 6 3 adc control lines, serial interface lines of usic1, timer control signals, ocds control port 7 5 adc control lines, serial interface lines of usic0, timer control signals, jtag, ocds control,system clock output port 10 16 address and/or data lines, bus control, serial interface lines of usic0, usic1 and can2, input/output lines for ccu60, jtag, ocds control port 15 5 analog input channels to adc1, timer control signals table 7 summary of the XC236X?s parallel ports (cont?d) port width alternate functions
xc2365 xc2000 family derivatives functional description preliminary data sheet 61 v0.1, 2007-06 draft version 3.16 instruction set summary table 8 lists the instructions of the XC236X in a condensed way. the various addressing modes that can be used wi th a specific instruction, the operation of the instructions, parameters for conditio nal execution of instructions, and the opcodes for each instruction can be found in the ?instruction set manual? . this document also provides a detailed description of each instruction. table 8 instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16-
xc2365 xc2000 family derivatives functional description preliminary data sheet 62 v0.1, 2007-06 draft version rol/ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 mov(b) move word (byte) data 2 / 4 movbs/z move byte operand to word op. with sign/zero extension 2 / 4 jmpa/i/r jump absolute/indirect/r elative if condition is met 4 jmps jump absolute to a code segment 4 jb(c) jump relative if direct bit is set (and clear bit) 4 jnb(s) jump relative if direct bit is not set (and set bit) 4 calla/i/r call absolute/indirect/relat ive subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push/pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret(p) return from intra-segment subroutine (and pop direct word register from system stack) 2 rets return from inter-segment subroutine 2 reti return from interrupt service subroutine 2 sbrk software break 2 srst software reset 4 idle enter idle mode 4 pwrdn unused instruction 1) 4 srvwdt service watchdog timer 4 diswdt/enwdt disable/enable watchdog timer 4 einit end-of-initialization register lock 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 table 8 instruction set summary (cont?d) mnemonic description bytes
xc2365 xc2000 family derivatives functional description preliminary data sheet 63 v0.1, 2007-06 draft version nop null operation 2 comul/comac multiply (and accumulate) 4 coadd/cosub add/subtract 4 co(a)shr (arithmetic) shift right 4 coshl shift left 4 coload/store load accumulator/store mac register 4 cocmp compare 4 comax/min maximum/minimum 4 coabs/cornd absolute value/round accumulator 4 comov data move 4 coneg/nop negate accumulator/null operation 4 1) the enter power down mode instruction is not used in the XC236X, due to the enhanced power control scheme. pwrdn will be correctly decoded, but will trigger no action. table 8 instruction set summary (cont?d) mnemonic description bytes
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 65 v0.1, 2007-06 draft version 4 electrical parameters the operating range for the XC236X is defined by its electrical parameters. for proper operation the indicated limitations must be respected when designing a system. attention: the parameters and values listed in the following sections of this preliminary data sheet are pre liminary and will be adjusted and amended after the complete device characterization has been completed. 4.1 general parameters these parameters are valid for all subsequent descriptions, unless otherwise noted. note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v ddp or v in < v ss ) the voltage on v ddp pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. table 9 absolute maximum rating parameters parameter symbol values unit note / test condition min. typ. max. storage temperature t st -65 ? 150 c ? junction temperature t j -40 ? 150 c under bias voltage on v ddi pins with respect to ground ( v ss ) v ddim , v ddi1 -0.5 ? 1.65 v ? voltage on v ddp pins with respect to ground ( v ss ) v ddpa , v ddpb -0.5 ? 6.0 v ? voltage on any pin with respect to ground ( v ss ) v in -0.5 ? v ddp + 0.5 v v in < v ddpmax input current on any pin during overload condition ?-10?10ma? absolute sum of all input currents during overload condition ? ? ? |100| ma ?
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 66 v0.1, 2007-06 draft version operating conditions the following operating conditions must not be exceeded to ensure correct operation of the XC236X. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. table 10 operating condition parameters parameter symbol values unit note / test condition min. typ. max. digital core supply voltage (if supplied externally) v ddi 1.4 ? 1.6 v core supply voltage difference ? v ddim - v ddi1 1) digital supply voltage for io pads and voltage regulators, upper voltage range v ddpa , v ddpb 4.5 ? 5.5 v 2) digital supply voltage for io pads and voltage regulators, lower voltage range v ddpa , v ddpb 3.0 ? 4.5 v 2) supply voltage difference ? v ddp - v ddi 3) digital ground voltage v ss 0 ? 0 v reference voltage overload current i ov -5 ? 5 ma per io pin 4)5) -2 ? 5 ma per analog input pin 4)5) overload positive current coupling factor for analog inputs 6) k ova ??1.0 i ov > 0 overload negative current coupling factor for analog inputs 6) k ova ??1.5 i ov < 0 overload positive current coupling factor for digital i/o pins 6) k ovd ??5.0 i ov > 0 overload negative current coupling factor for digital i/o pins 6) k ovd ??1.0 i ov < 0
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 67 v0.1, 2007-06 draft version absolute sum of overload currents c l ? 20 ? pf pin drivers in default mode 7) voltage regulator buffer capacitance for dmp_m c evrm 1.0 ? 4.7 c evr1 470 ? 2200 nf one for each supply pin 8) ambient temperature t a ???csee table 1 1) in case both core power domains are clocked, the difference between the power supply voltages must be less than 10mv. this condition imposes additional constraints when using external power supplies. in order to supply both core power domains, two independent external voltage regulators may not be used. the simplest possibility is to supply both power domains directly via a single external power supply. 2) performance of pad drivers, a/d converter, and flash module depends on v ddp . 3) this limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down, and power-save modes, if v ddi is supplied externally. 4) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range: v ov > v ihmax ( i ov >0) or v ov < v ilmin ( i ov < 0). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltages must remain within the specified limits. proper operation under overload conditions depends on the application. overload conditions must not occur on pin xtal1 (powered by v ddi ). 5) not subject to production test - verified by design/characterization. 6) an overload current ( i ov ) through a pin injects a certain error current ( i inj ) into the adjacent pins. this error current adds to the respective pin?s leakage current ( i oz ). the amount of error current depends on the overload current and is defined by the overload coupling factor k ov . the polarity of the injected error current is inverse compared to the polarity of the overload current that produces it. the total current through a pin is | i tot | = | i oz | + (| i ov | k ov ). the additional error current may distort the input voltage on analog inputs. 7) the timing is valid for pin drivers operating in default current mode (selected after reset). reducing the output current may lead to increased delays or reduced driving capability ( c l ). 8) to ensure the stability of the voltage regulators the evrs must be buffered with ceramic capacitors. separate buffer capacitors with the recomended values shall be connected to each v ddi pin as close as possible to the pins to keep the resistance of the board tracks below 2 ? table 10 operating condition parameters (cont?d) parameter symbol values unit note / test condition min. typ. max.
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 68 v0.1, 2007-06 draft version parameter interpretation the parameters listed in the following partly represent the characteristics of the XC236X and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the XC236X will provide signals with the respective characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective characteristics to the XC236X.
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 69 v0.1, 2007-06 draft version 4.2 dc parameters these parameters are static or average values, which may be exceeded during switching transitions (e.g. output current). the XC236X can operate within a wide supply voltage range from 3.0 v to 5.5 v. however, during operation this supply voltage must not vary within the complete operating voltage range, but must remain within a certain band of 10% of the chosen nominal supply voltage. for this reason and because the electrical behaviour partly depends on the supply voltage, the parameters are specified twice for the upper and the lower voltage area. during operation, the supply voltages may only change with a maximum speed of dv/dt < 1 v/ms. the leakage currents strongly depend on the operating temperature and the actual voltage level at the respective pin. the maximum values given in the following tables apply under worst case conditions, i.e. maximum temperature and an input level equal to the supply voltage. the actual value for the leakage current ca n be determined by evaluating the respective leakage derating formula (see tables) usi ng values from the actual application. the pads of the XC236X are designed to ope rate in various driver modes. the dc parameter specifications refer to the current limits given in table 11 . table 11 current limits for port output drivers port output driver mode maximum output current ( i olmax , - i ohmax ) 1) 1) an output current above | i oxnom | may be drawn from up to three pins at the same time. for any group of 16 neighboring output pins the total output current in each direction ( nominal output current ( i olnom , - i ohnom ) v ddp 4.5 v v ddp < 4.5 v v ddp 4.5 v v ddp < 4.5 v strong driver 10 ma 10 ma 2.5 ma 2.5 ma medium driver 4.0 ma 2.5 ma 1.0 ma 1.0 ma weak driver 0.5 ma 0.5 ma 0.1 ma 0.1 ma
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 70 v0.1, 2007-06 draft version 4.2.1 dc parameters for upper voltage area these parameters apply to the upper io voltage area of 4.5 v v ddp table 12 dc characteristics for 4.5 v v ddp 5.5 v (operating conditions apply) 1) parameter symbol values unit note / test condition min. typ. max. input low voltage (all except xtal1) v il sr -0.3 ? 0.3 v ddp v? input low voltage for xtal1 v ilc sr -1.7 + v ddi ?0.3 v ddi v? input high voltage (all except xtal1) v ih sr 0.7 v ddp ? v ddp + 0.3 v? input high voltage for xtal1 v ihc sr 0.7 v ddi ?1.7v 2) input hysteresis 3) hys cc 0.11 v ddp ??v v dd in [v], series resistance = 0 ? v ol cc ? ? 1.0 v i ol i olmax 4) output low voltage v ol cc ? ? 0.4 v i ol i olnom 4) 5) output high voltage 6) v oh cc v ddp - 1.0 ??v i oh i ohmax 4) output high voltage 6) v oh cc v ddp - 0.4 ??v i oh i ohnom 4) 5) input leakage current (port 5, port 15) 7) i oz1 cc ? v in < v ddp input leakage current (all other) 7)8) i oz2 cc ? t j v in < v ddp input leakage current (all other) 7)8) i oz2 cc ? t j v in < v ddp level inactive hold current i lhi ??-30 v out v ihmin level active hold current i lha -220 ? ? v out v ilmax
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 71 v0.1, 2007-06 draft version xtal1 input current i il cc ? ? v in < v ddi pin capacitance 9) (digital inputs/outputs) c io cc ? ? 10 pf 1) keeping signal levels within the limits specified in th is table, ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . 2) overload conditions must not occur on pin xtal1. 3) not subject to production test - verified by design/characterization. hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. it cannot suppress switching due to external system noise under all conditions. 4) the maximum deliverable output current of a port driver depends on the selected output driver mode, see table 11 , current limits for port output drivers . the limit for pin groups must be respected. 5) as a rule, with decreasing output current the output levels approach the respective supply level ( v ol v ss , v oh v ddp ). however, only the levels for nominal output currents are verified. 6) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 7) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. please refer to the definition of the overload coupling factor k ov . 8) the given values are worst-case values. in the production test, this leakage current value is only tested at 125c, other values are ensured via correlation. for derating, please refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.009 e (0.054tj) [ v ddp - v pin [v]): i oz = i oztempmax - (1.6 dv) [ table 12 dc characteristics for 4.5 v v ddp 5.5 v (cont?d) (operating conditions apply) 1) parameter symbol values unit note / test condition min. typ. max.
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 72 v0.1, 2007-06 draft version 4.2.2 dc parameters for lower voltage area these parameters apply to the lower io voltage area of 3.0 v v ddp table 13 dc characteristics for 3.0 v v ddp 4.5 v (operating conditions apply) 1) parameter symbol values unit note / test condition min. typ. max. input low voltage (all except xtal1) v il sr -0.3 ? 0.3 v ddp v? input low voltage for xtal1 v ilc sr -1.7 + v ddi ?0.3 v ddi v? input high voltage (all except xtal1) v ih sr 0.7 v ddp ? v ddp + 0.3 v? input high voltage for xtal1 v ihc sr 0.7 v ddi ?1.7v 2) input hysteresis 3) hys cc 0.11 v ddp ??v v dd in [v], series resistance = 0 ? v ol cc ? ? 1.0 v i ol i olmax 4) output low voltage v ol cc ? ? 0.4 v i ol i olnom 4) 5) output high voltage 6) v oh cc v ddp - 1.0 ??v i oh i ohmax 4) output high voltage 6) v oh cc v ddp - 0.4 ??v i oh i ohnom 4) 5) input leakage current (port 5, port 15) 7) i oz1 cc ? v in < v ddp input leakage current (all other) 7)8) i oz2 cc ? t j v in < v ddp input leakage current (all other) 7)8) i oz2 cc ? t j v in < v ddp level inactive hold current i lhi ??-10 v out v ihmin level active hold current i lha -150 ? ? v out v ilmax
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 73 v0.1, 2007-06 draft version xtal1 input current i il cc ? ? v in < v ddi pin capacitance 9) (digital inputs/outputs) c io cc ? ? 10 pf 1) keeping signal levels within the limits specified in th is table, ensures operation without overload conditions. for signal levels outside these specifications, also refer to the specification of the overload current i ov . 2) overload conditions must not occur on pin xtal1. 3) not subject to production test - verified by design/characterization. hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. it cannot suppress switching due to external system noise under all conditions. 4) the maximum deliverable output current of a port driver depends on the selected output driver mode, see table 11 , current limits for port output drivers . the limit for pin groups must be respected. 5) as a rule, with decreasing output current the output levels approach the respective supply level ( v ol v ss , v oh v ddp ). however, only the levels for nominal output currents are verified. 6) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 7) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. please refer to the definition of the overload coupling factor k ov . the leakage current value is not tested in the lower voltage range, but only in the upper voltage range. this parameter is ensured via correlation. 8) the given values are worst-case values. in the production test, this leakage current value is only tested at 125c, other values are ensured via correlation. for derating, please refer to the following descriptions: leakage derating depending on temperature ( t j = junction temperature [c]): i oz = 0.005 e (0.054tj) [ v ddp - v pin [v]): i oz = i oztempmax - (1.3 dv) [ table 13 dc characteristics for 3.0 v v ddp 4.5 v (cont?d) (operating conditions apply) 1) parameter symbol values unit note / test condition min. typ. max.
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 74 v0.1, 2007-06 draft version 4.2.3 power consumption the amount of power that is consumed by the XC236X depends on several factors, such as supply voltage, operating frequency, amount of active circuitry, and operating temperature. part of this depends on the device?s activity (switching current), part of this is independent (leakage current). therefore, the leakage current must be added to all other (frequency-dependent) parameters. for additional information, please refer to section 5.2 , thermal considerations . table 14 power consumption XC236X (operating conditions apply) parameter sym- bol values unit note / test condition min. typ. max. supply current caused by leakage 1) (dmp_1 powered) 1) the supply current caused by leakage mainly depends on the junction temperature (see figure 12 ) and the supply voltage. the temperature difference between the junction temperature t j and the ambient temperature t a must be taken into account. as this fraction of the supply current does not depend on the device?s activity, it must be added to each other power consumption parameter. i ddl ? 600,000 v ddp = v ddpmax 2) t j ), t j in [ v ddp - 0.1 v to v ddp , all outputs (including pins configured as outputs) disconnected. this parameter is tested at 25 t j i ddl ? 500,000 v ddp = v ddpmax 2) t j ), t j in [ i ddp ? 10 + 0.6 f sys tbd ma active mode 3) f sys in [mhz] 3) the pad supply voltage pins ( v ddp ) provide the input current for the on-chip evvrs and the current consumed by the pin output drivers. a small amount of current is consumed because the drivers? input stages are switched.
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 75 v0.1, 2007-06 draft version figure 12 leakage supply current as a function of temperature mc_xc2x_iddl_np t j [c] i ddl [ma] 2 4 6 050 150 100 -50
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 76 v0.1, 2007-06 draft version figure 13 supply current in active mo de as a function of frequency mc_xc2x_idd f sys [mhz] i dd [ma] 10 20 30 20 40 80 60 40 50 60 80 100 i ddtyp
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 77 v0.1, 2007-06 draft version 4.3 analog/digital converter parameters these parameters describe how the optimum adc performance can be reached. table 15 a/d converter characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. analog reference supply v aref sr v agnd + 1.0 v ddpa + 0.05 v 1) 1) tue is tested at v arefx = v ddpa , v agnd = 0 v. it is verified by design for all other voltages within the defined voltage range. the specified tue is valid only, if the absolute sum of input overload currents on port 5 or port 15 pins (see i ov specification) does not exceed 10 ma, and if v aref and v agnd remain stable during the respective period of time. analog reference ground v agnd sr v ss - 0.05 v aref - 1.0 v? analog input voltage range v ain sr v agnd v aref v 2) 2) v ain may exceed v agnd or v arefx up to the absolute maximum ratings. ho wever, the conversion result in these cases will be x000 h or x3ff h , respectively. basic clock frequency f adci 0.5 16.5 mhz 3) 3) the limit values for f adci must not be exceeded when selecting the peripheral frequency and the prescaler setting. conversion time for 10-bit result 4) t c10 cc (17 + stc) t adci ?? conversion time for 8-bit result 4) t c8 cc (15 + stc) t adci ?? total unadjusted error tue cc ? c aint cc ? 15 pf 5) switched capacitance of an analog input c ains cc ? 7 pf 5) resistance of the analog input path r ain cc ? 1.5 k ? c areft cc ? 20 pf 5) switched capacitance of the reference input c arefs cc ? 20 pf 5) resistance of the reference input path r aref cc ? 2 k ?
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 78 v0.1, 2007-06 draft version figure 14 equivalent circuitry for analog inputs 4) this parameter includes the sample time (also the ad ditional sample time specified by stc), the time for determining the digital result and the time to load the result register with the conversion result. values for the basic clock t adci depend on programming and can be taken from table 16 . 5) not subject to production test - verified by design/characterization. the given parameter values cover the complete operating range. under relaxed operating conditions (temperature, supply voltage) reduced values can be used for calculations. at room temperature and nominal supply voltage the following typical values can be used: c ainttyp = 12 pf, c ainstyp = 5 pf, r aintyp = 1.0 k ? c arefttyp = 15 pf, c arefstyp = 10 pf, r areftyp = 1.0 k ? r source v ain c ext c aint c ains - r ain, on c ains
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 79 v0.1, 2007-06 draft version sample time and conversion time of the XC236X?s a/d converters are programmable. the above timing can be calculated using table 16 . the limit values for f adci must not be exceeded when selecting the prescaler value. converter timing example: converter timing example: table 16 a/d converter computation table globctr.5-0 (diva) a/d converter basic clock f adci inpcrx.7-0 (stc) sample time t s 000000 b f sys 00 h t adci f sys / 2 01 h t adci f sys / 3 02 h t adci f sys / (diva+1) : t adci f sys / 63 fe h t adci f sys / 64 ff h t adci f sys = 66 mhz (i.e. t sys = 15.2 ns), diva = 03 h , stc = 00 h basic clock f adci = f sys / 4 = 16.5 mhz, i.e. t adci = 60.6 ns sample time t s = t adci conversion 10-bit: t c10 = 17 t adci = 17 conversion 8-bit: t c8 = 15 t adci = 15 f sys = 40 mhz (i.e. t sys = 25 ns), diva = 02 h , stc = 03 h basic clock f adci = f sys / 3 = 13.3 mhz, i.e. t adci = 75 ns sample time t s = t adci conversion 10-bit: t c10 = 20 t adci = 20 conversion 8-bit: t c8 = 18 t adci = 18
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 80 v0.1, 2007-06 draft version 4.4 ac parameters these parameters describe the dynamic behavior of the XC236X. 4.4.1 definition of internal timing the internal operation of the XC236X is controlled by the internal system clock f sys . because the system clock signal f sys can be generated from several internal and external sources via different mechanisms, the duration of system clock periods (tcss) and their variation (and also the derived external timing) depend on the used mechanism to generate f sys . this influence must be regarded when calculating the timings for the XC236X. figure 15 generation mechanisms for the system clock note: the example for pll operation shown in figure 15 refers to a pll factor of 1:4, the example for prescaler operation refers to a divider factor of 2:1. mc_xc2x_clockgen phase locked loop operation (1:n) f in direct clock drive (1:1) prescaler operation (n:1) f sys f in f sys f in f sys tcs tcs tcs
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 81 v0.1, 2007-06 draft version the specification of the external timing (a c characteristics) depends on the period of the system clock (tcs). direct drive when direct drive operation is configured (syscon0.clksel = 11 b ), the system clock is derived directly from the input clock signal dirin: f sys = f in . the frequency of f sys directly follows the frequency of f in . in this case, the high and low time of f sys is defined by the duty cycle of the input clock f in . a similar configuration can be achieved by selecting the xtal1 1) input. prescaler operation when prescaler operation is configured (syscon0.clksel = 10 b , pllcon0.vcoby = 1 b ), the system clock is derived either from the crystal oscillator (input clock signal xtal1) or from the internal clock source through the output-prescaler: f sys = f osc / (k1div + 1). if the divider factor is selected as 1, the frequency of f sys directly follows the frequency of f osc . in this case, the high and low time of f sys is defined by the duty cycle of the input clock f osc (external or internal). the lowest system clock frequency can be achieved in this mode by selecting the maximum value for divider factor k1: f sys = f osc / 1024. phase locked loop (pll) when pll operation is configured (syscon0.clksel = 10 b , pllcon0.vcoby = 0 b ), the on-chip phase locked loop provides the system clock. the pll multiplies the selected input frequency by the factor f ( f sys = f in f ), which results from the input divider (p), the multiplication factor (n), and the output divider (k2): ( f = n+1 / (p+1 f sys is constantly adjusted so it is locked to f in . the slight variation causes a jitter of f sys which also affects the duration of individual tcss. 1) voltages on xtal1 must comply to the core supply voltage v ddi1 .
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 82 v0.1, 2007-06 draft version the timing listed in the ac characteristics refers to tcss. therefore, the timing must be calculated using the minimum tcs possible under the respective circumstances. the actual minimum value for tcs depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator), the accumulated jitter is limited, which means that the relative deviation for periods of more than one tcs is lower than for one single tcs. this is especially important for bus cycles us ing waitstates and e.g. for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is, therefore, negligible. the value of the accumulated pll jitter depends on the number of consecutive vco output cycles within the respective timeframe. the vco output clock is divided by the output prescaler (k2+1) to generate the system clock signal f sys . therefore, the number of vco cycles can be represented as (k2+1) t , where t is the number of consecutive f sys cycles (tcs). different frequency bands can be selected for the vco, so the operation of the pll can be adjusted to a wide range of input and output frequencies: wakeup clock when wakeup operation is configured (syscon0.clksel = 00 b ), the system clock is derived from the low-frequency wakeup clock source: f sys = f wu . in this mode, a basic functionality can be maintained without requiring an external clock source and while minimizing the power consumption. table 17 vco bands for pll operation 1) 1) not subject to production test - verified by design/characterization. pllcon0.vcosel vco frequency range base frequency range 00 40 ? 120 mhz 10 ? 40 mhz 01 90 ? 160 mhz 20 ? 80 mhz 1x reserved
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 83 v0.1, 2007-06 draft version selecting and changing the operating frequency when selecting a clock source and the clock generation method, the required parameters must be carefully written to the respective bitfields, to avoid unintended intermediate states. many applications change the frequency of the system clock ( f sys ) during the operation, to optimize performance and po wer consumption of the system. changing the operating frequency also changes the consumed switching current, which influences the power supply. therefore, while the core voltage is generated by the on-chip evrs, the operating frequency may only be changed by factors of 5 maximum, or in steps of 20 mhz maximum, whatever condition is tighter. to avoid the indicated problems, recommended sequences are provided which ensure the intended operation of the clock system interacting with the power system. 4.4.2 on-chip flash operation accesses to the XC236X?s flash modules are controlled by the imb. built-in prefetching mechanisms optimize the performance for sequential accesses. table 18 flash characteristics (operating conditions apply) parameter symbol limit values unit min. typ. max. programming time per 128-byte page t pr cc ? 3 1) 1) programming and erase times depend on the internal flash clock source. the control state machine needs a few system clock cycles, which only becomes relevant for extremely low system frequencies. tbd ms erase time per sector/page t er cc ? 4 1) tbd ms
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 84 v0.1, 2007-06 draft version 4.4.3 external clock drive these parameters define the external clock supply for the XC236X. the clock signal can be supplied either to pin p2.9 or to pin xtal1. figure 16 external clock drive xtal1 note: if the on-chip oscillator is used together with a crystal or a ceramic resonator, the oscillator frequency is limited to a range of 4 mhz to 16 mhz. it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimum parameters for the oscillator operation. please refer to the limits specified by the crystal supplier. when driven by an external clock signal it will accept the specified input frequency range. operation at input frequencies below 4 mhz is possible but is verified by design only (not subject to production test). table 19 external clock drive characteristics (operating conditions apply) parameter symbol limit values unit min. max. oscillator period t osc sr 25 250 1) 1) the maximum limit is only relevant for pll operation to ensure the minimum input frequency for the pll. ns high time 2) 2) the clock input signal must reach the defined levels v ilc and v ihc (for xtal1) or v il and v ih for p2.9. t 1 sr6?ns low time 2) t 2 sr6?ns rise time 2) t 3 sr?8ns fall time 2) t 4 sr?8ns mct05572 t 1 t 2 t osc t 3 t 4 0.5 v ddi v ilc v ihc
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 85 v0.1, 2007-06 draft version 4.4.4 testing waveforms these references are used for characterization and production testing (except for pin xtal1). figure 17 input output waveforms figure 18 float waveforms mcd05556c 0.3 v ddp input signal (driven by tester) output signal (measured) hold time output delay output delay hold time output timings refer to the rising edge of clkout. input timings are calculated from the time, when the input signal reaches v ih or v il , respectively. 0.2 v ddp 0.8 v ddp 0.7 v ddp mca05565 timing reference points v load + 0.1 v v load - 0.1 v v oh - 0.1 v v ol + 0.1 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded v oh / v ol level occurs ( i oh / i ol = 20 ma).
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 86 v0.1, 2007-06 draft version 4.4.5 external bus timing the following parameters define the behavior of the XC236X?s bus interface. figure 19 clkout signal timing note: the term clkout refers to the reference clock output signal which is generated by selecting f sys as source signal for the clock output signal extclk on pin p2.8 and by enabling the high-speed clock driver on this pin. table 20 clkout reference signal parameter symbol limits unit min. max. clkout cycle time tc 5 cc 40/25/15 1) 1) the clkout cycle time is in fluenced by the pll jitter (given values apply to f cpu = 25/40/66 mhz). for longer periods the relative deviation decreases (see pll deviation formula). ns clkout high time tc 6 cc 3 ? ns clkout low time tc 7 cc 3 ? ns clkout rise time tc 8 cc ? 3 ns clkout fall time tc 9 cc ? 3 ns mct05571 clkout t c5 t c6 t c7 t c8 t c9
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 87 v0.1, 2007-06 draft version variable memory cycles external bus cycles of the XC236X are exec uted in five subsequent cycle phases (ab, c, d, e, f). the duration of each cycle phase is programmable (via the tconcsx registers) to adapt the external bus cycles to the respective external module (memory, peripheral, etc.). the duration of the access phase can optionally be controlled by the external module via the ready handshake input. this table provides a summary of the phases and the respective choices for their duration. note: the bandwidth of a parameter (minimum and maximum value) covers the whole operating range (temperature, voltage) as well as process variations. within a given device, however, this bandwidth is smaller than the specified range. this is also due to interdependencies between certain parameters. some of these interdependencies are described in additional notes (see standard timing). timing values are listed in table 22 and table 23 . the shaded parameters have been verified by characterization. they are not subject to production test. table 21 programmable bus cycle phases (see timing diagrams) bus cycle phase parameter valid values unit address setup phase, the standard duration of this phase (1 ? 2 tcs) can be extended by 0 ? 3 tcs if the address window is changed tpab 1 ? 2 (5) tcs command delay phase tpc 0 ? 3 tcs write data setup/mux tristate phase tpd 0 ? 1 tcs access phase tpe 1 ? 32 tcs address/write data hold phase tpf 0 ? 3 tcs
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 88 v0.1, 2007-06 draft version table 22 external bus cycle timing for 4.5 v v ddp 5.5 v (operating conditions apply) parameter symbol limits unit note min. typ. max. output valid delay for: rd , wr (l /h ) tc 10 cc ? 13 ns output valid delay for: bhe , ale tc 11 cc ? 13 ns output valid delay for: a23 ? a16, a15 ? a0 (on p0/p1) tc 12 cc ? 14 ns output valid delay for: a15 ? a0 (on p2/p10) tc 13 cc ? 14 ns output valid delay for: cs tc 14 cc ? 13 ns output valid delay for: d15 ? d0 (write data, mux-mode) tc 15 cc ? 14 ns output valid delay for: d15 ? d0 (write data, demux- mode) tc 16 cc ? 14 ns output hold time for: rd , wr (l /h ) tc 20 cc 0 8ns output hold time for: bhe , ale tc 21 cc 0 8ns output hold time for: a23 ? a16, a15 ? a0 (on p2/p10) tc 23 cc 0 8ns output hold time for: cs tc 24 cc 0 8ns output hold time for: d15 ? d0 (write data) tc 25 cc 0 8ns input setup time for: ready, d15 ? d0 (read data) tc 30 sr 18 ?ns input hold time for: ready, d15 ? d0 (read data) 1) 1) read data are latched with the same (internal) clock edge that triggers the address change and the rising edge of rd . therefore address changes before the end of rd have no impact on (demultiplexed) read cycles. read data can be removed after the rising edge of rd . tc 31 sr -4 ?ns
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 89 v0.1, 2007-06 draft version table 23 external bus cycle timing for 3.0 v v ddp 4.5 v (operating conditions apply) parameter symbol limits unit note min. typ. max. output valid delay for: rd , wr (l /h ) tc 10 cc ? 20 ns output valid delay for: bhe , ale tc 11 cc ? 20 ns output valid delay for: a23 ? a16, a15 ? a0 (on p0/p1) tc 12 cc ? 22 ns output valid delay for: a15 ? a0 (on p2/p10) tc 13 cc ? 22 ns output valid delay for: cs tc 14 cc ? 20 ns output valid delay for: d15 ? d0 (write data, mux-mode) tc 15 cc ? 21 ns output valid delay for: d15 ? d0 (write data, demux- mode) tc 16 cc ? 21 ns output hold time for: rd , wr (l /h ) tc 20 cc 0 10 ns output hold time for: bhe , ale tc 21 cc 0 10 ns output hold time for: a23 ? a16, a15 ? a0 (on p2/p10) tc 23 cc 0 10 ns output hold time for: cs tc 24 cc 0 10 ns output hold time for: d15 ? d0 (write data) tc 25 cc 0 10 ns input setup time for: ready, d15 ? d0 (read data) tc 30 sr 29 ?ns input hold time for: ready, d15 ? d0 (read data) 1) 1) read data are latched with the same (internal) clock edge that triggers the address change and the rising edge of rd . therefore address changes before the end of rd have no impact on (demultiplexed) read cycles. read data can be removed after the rising edge of rd . tc 31 sr -6 ?ns
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 90 v0.1, 2007-06 draft version figure 20 multiplexed bus cycle clkout tp ab tp c tp d tp e tp f ale tc 21 tc 11 a23-a16, bhe, csx tc 11 / tc 14 rd wr(l/h) tc 20 tc 10 data in ad15-ad0 (read) tc 30 tc 31 mct05557 ad15-ad0 (write) tc 13 tc 15 tc 25 tc 13 tc 23 data out low address high address low address
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 91 v0.1, 2007-06 draft version figure 21 demultiplexed bus cycle address tp ab tp c tp d tp e tp f tc 21 tc 11 tc 11 / tc 14 tc 20 tc 10 data in tc 30 tc 31 mct05558 tc 16 tc 25 clkout ale a23-a0, bhe, csx rd wr(l/h) d15-d0 (read) d15-d0 (write) data out
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 92 v0.1, 2007-06 draft version bus cycle control via ready input the duration of an external bus cycle can be c ontrolled by the exter nal circuitry via the ready input signal. the polarity of this input signal can be selected. synchronous ready permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal clkout. asynchronous ready puts no timing constraints on the input signal but incurs one waitstate minimum due to the additional synchronization stage. the minimum duration of an asynchronous ready signal to be safely synchronized must be one clkout period plus the input setup time. an active ready signal can be deactivated in response to the trailing (rising) edge of the corresponding command (rd or wr ). if the next following bus cycle is ready-cont rolled, an active ready signal must be disabled before the first valid sample point for the next bus cycle. this sample point depends on the programmed phases of the next following cycle.
xc2365 xc2000 family derivatives electrical parameters preliminary data sheet 93 v0.1, 2007-06 draft version figure 22 ready timing note: if the ready input is sampled inactive at the indicated sampling point (?not rdy?) a ready-controlled waitstate is inserted (tprdy), sampling the ready input active at the indicated sampling point (?ready?) terminates the currently running bus cycle. note the different sampling points for synchronous and asynchronous ready. this example uses one mandatory waitstate (see tpe) before the ready input is evaluated. mct05559 ready asynchron. not rdy ready data out tc 25 tc 30 d15-d0 (write) ready synchronous not rdy ready data in d15-d0 (read) tc 10 rd, wr tp d tp e tp rdy tp f clkout tc 20 tc 30 tc 31 tc 31 tc 30 tc 31 tc 30 tc 31 tc 30 tc 31
xc2365 xc2000 family derivatives package and reliability preliminary data sheet 94 v0.1, 2007-06 draft version 5 package and reliability in addition to the electrical parameters, the following information ensures proper integration of the XC236X into the target system. 5.1 packaging these parameters describe the housing rather than the silicon. table 24 package parameters (pg-lqfp-100) parameter symbol limit values unit notes min. max. exposed pad dimension ex p diss ?1.0w? thermal resistance junction-ambient r
xc2365 xc2000 family derivatives package and reliability preliminary data sheet 95 v0.1, 2007-06 draft version package outlines figure 23 pg-lqfp-100 (plastic green thin quad flat package) you can find all of our packages, sorts of packing and others in our infineon internet page ?packages?: http://www.infineon.com/packages dimensions in mm.
xc2365 xc2000 family derivatives package and reliability preliminary data sheet 96 v0.1, 2007-06 draft version 5.2 thermal considerations when operating the XC236X in a system, the total heat generated on the chip must be dissipated to the ambient environment to prevent overheating and resulting thermal damages. the maximum heat that can be dissipated depends on the package and its integration into the target board. the ?thermal resistance r ? p int + p iostat + p iodyn ) r p int = v ddp i ddp (see table 14 ). the static external power consumption caused by the output drivers is defined as p iostat = v ddp - v oh ) i oh ) + v ol i ol ) the dynamic external power consumpt ion caused by the output drivers ( p iodyn ) depends on the capacitive load connected to the re spective pins and the switching frequencies. if the total power dissipation determined fo r a given system configuration exceeds the defined limit countermeasures must be ta ken to ensure prope r system operation: ? reduce v ddp , if possible in the system ? reduce the system frequency ? reduce the number of output pins ? reduce the load on active output drivers
xc2365 xc2000 family derivatives package and reliability preliminary data sheet 97 v0.1, 2007-06 draft version 5.3 flash memory parameters the data retention time of the XC236X?s flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the flash memory has been erased and programmed. table 25 flash parameters (XC236X, 768 kbytes) parameter symbol limit values unit notes min. max. data retention time t ret 20 ? years 10 3 erase/program cycles flash erase endurance n er 15
www.infineon.com published by infineon technologies ag

▲Up To Search▲

Price & Availability of XC236X

	To Download XC236X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .